----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:14:38 04/17/2008 
-- Design Name: 
-- Module Name:    fiber_encode - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fiber_encode is
    Port ( clk40 : in  STD_LOGIC;
           clk160 : in  STD_LOGIC;
           LUT_data : in  STD_LOGIC_VECTOR (3 downto 0);
			  clk_en_first_Bit_marker : in STD_LOGIC;
           encoded_signal : out  STD_LOGIC;
			  reset : in std_logic);
end fiber_encode;

architecture Behavioral of fiber_encode is
   signal counter: std_logic_vector(1 downto 0);
	signal counter_reset: std_logic;
	signal regsig0, regsig1, regsig2, regsig3, fifo_reset: std_logic;
	signal encoded_signal_prereg: std_logic;
	signal clk_en_first_bit_marker_reg: std_logic;
	
begin
   process(clk160, reset, clk_en_first_bit_marker)
	begin
	   if reset = '1' then
	      clk_en_first_bit_marker_reg <= '0';
	   elsif clk160'event and clk160='1' then
	      clk_en_first_bit_marker_reg <= clk_en_first_bit_marker;
	   end if;
	end process;
   -- counter for mux switching
	-- be careful write all signals in the sensitivity list, otherwise 
   -- the adder is 0 to 1 which results in swaped 2Bit and 8Bist
   process(clk160, reset, clk_en_first_bit_marker_reg, counter)
	begin
	   if reset='1' then
		   counter <= "00";
	   elsif clk160'event and clk160 = '1' then
		   if clk_en_first_Bit_marker_reg = '1' then
			   counter <= "00";
	      else
			   counter <= counter + '1';
			end if;
		end if;
	end process;
	
-- mux for serialization MSB
	process(counter(1 downto 0), LUT_data)
	begin
      case (counter(1 downto 0)) is 
         when "00" =>
            encoded_signal_prereg<= LUT_data(3);
         when "01" =>
            encoded_signal_prereg<= LUT_data(2);
         when "10" =>
            encoded_signal_prereg<= LUT_data(1);
         when "11" =>
            encoded_signal_prereg<= LUT_data(0);
         when others =>
            encoded_signal_prereg<= LUT_data(0);
      end case;	
	end process;

   -- final register for heat stable timing, register in the IO cell
	-- there is so much asyncronous logic befor this register, so it will not add much
	-- additional delay, since it runs with 160 MHz
   process(encoded_signal_prereg, clk160)
	begin
	   if clk160'event and clk160 = '1' then
		   encoded_signal <= encoded_signal_prereg;
	   end if;
	end process;
	
-- debug for regularly flipflop reseting / loading
--   process(counter_int)
--	begin
--      if counter_int = 0 then 
--		   fifo_reset <= '1';
--   	else 
--		   fifo_reset <= '0';
--		end if;
--   end process;
	
--   process(clk40, fifo_reset)
--	begin
--	if fifo_reset = '1' then
--	   regsig0 <= '1';
--  elsif clk160'event and clk160 <= '0' then
--	   regsig0 <= regsig1;
--	end if;
--	end process;
	
--	   process(clk40, fifo_reset)
--	begin
--	if fifo_reset = '1' then
--	   regsig1 <= '1';
--   elsif clk160'event and clk160 <= '0' then
--	   regsig1 <= regsig2;
--	end if;
--	end process;
	
--	   process(clk40, fifo_reset)
--	begin
--	if fifo_reset = '1' then
--	   regsig2 <= '0';
--  elsif clk160'event and clk160 <= '0' then
--	   regsig2 <= regsig3;
--	end if;
--	end process;

--	   process(clk40, fifo_reset)
--	begin
--	if fifo_reset = '1' then
--	   regsig3 <= '0';
--   elsif clk160'event and clk160 <= '0' then
--	   regsig3 <= '0';
--	end if;
--	end process;
	
--   encoded_signal <= regsig0;
	
   -- flipflop for syncronizing with clk40
	--process(clk40, clk160)
	--begin
	   --if clk160 = '0' then
		  -- counter_reset <= '0';
		--elsif clk40'event and clk40 = '1' then
		 --  counter_reset <= '1';
		--end if;
	--end process;
	
end Behavioral;