----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Stefan Zimmer
-- 
-- Create Date:    19:15:04 04/16/2008 
-- Design Name: 
-- Module Name:    LUT_module_CBTOF - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity LUT_module_CBC is
    Port ( T0_trigger : in  STD_LOGIC;
           V0_trigger : in  STD_LOGIC;
			  V1_trigger : in  STD_LOGIC;
			  V2_trigger : in  STD_LOGIC;
			  V3_trigger : in  STD_LOGIC;
           trigger : out STD_LOGIC_vector(3 downto 0);
			  clk160 : in  STD_LOGIC;
			  clk120 : in STD_LOGIC;
           clk_ro_en_minus180_reg : in STD_Logic;
			  clk_ro_en_reg : in STD_LOGIC;
			  reset : in STD_LOGIC;
			  LUT_address : in std_logic_vector(11 downto 0);
			  LUT_data_in : in std_logic_vector(3 downto 0);
			  LUT_we : in std_logic;
			  LUT_data_out: out std_logic_vector(3 downto 0);
			  T0_parallized : out std_logic_vector(1 downto 0);
			  V0_parallized : out std_logic_vector(1 downto 0);
			  V1_parallized : out std_logic_vector(1 downto 0);
			  V2_parallized : out std_logic_vector(1 downto 0);
			  V3_parallized : out std_logic_vector(1 downto 0)
			  );
end LUT_module_CBC;

architecture Behavioral of LUT_module_CBC is
signal trigger_signal: std_logic_vector(3 downto 0);
signal T0_signal: std_logic_vector(1 downto 0);
signal T0_reg : std_logic;
signal V0_signal: std_logic_vector(1 downto 0);
signal V0_reg : std_logic;
signal V1_signal: std_logic_vector(1 downto 0);
signal V1_reg : std_logic;
signal V2_signal: std_logic_vector(1 downto 0);
signal V2_reg : std_logic;
signal V3_signal: std_logic_vector(1 downto 0);
signal V3_reg : std_logic;
signal clk_ro_en: std_logic;
signal clk_ro_en_minus180: std_logic;

	
begin

   process(clk160, clk_ro_en_reg, reset)
	begin
	   if reset = '1' then
		   clk_ro_en <= '0';
		elsif clk160'event and clk160 = '0' then
		   clk_ro_en <= clk_ro_en_reg;
		end if;
	end process;
	
	-- RAMB16_S1_S1_inst : RAMB16_S1_S1 synthesis tool has problems with it see mikrokontroller.net
	
	-- paralizer for T0 trigger assuming MSB logic
	process(clk160, reset, T0_trigger)
	begin
	   if reset = '1' then
		   T0_signal(1) <= '0';
		elsif clk160'event and clk160 = '1' and clk_ro_en = '1' then
		   T0_signal(1) <= T0_trigger;
		end if;
	end process;
	
	process(clk160, reset, T0_trigger)
	begin
	   if reset = '1' then
		   T0_reg <= '0';
		elsif clk160'event and clk160 = '1' then
		   T0_reg <= T0_trigger;
		end if;
	end process;
	
	process(clk160, reset, T0_reg, clk_ro_en)
	begin
	   if reset = '1' then
		   T0_signal(0) <= '0';
		elsif clk160'event and clk160 = '1' and clk_ro_en = '1' then
		   T0_signal(0) <= T0_reg;
		end if;
	end process;
	T0_parallized <= T0_signal;
	
		-- paralizer for V0 trigger assuming MSB logic
	process(clk160, reset, V0_trigger)
	begin
	   if reset = '1' then
		   V0_signal(1) <= '0';
		elsif clk160'event and clk160 = '1' and clk_ro_en = '1' then
		   V0_signal(1) <= V0_trigger;
		end if;
	end process;
	
	process(clk160, reset, V0_trigger)
	begin
	   if reset = '1' then
		   V0_reg <= '0';
		elsif clk160'event and clk160 = '1' then
		   V0_reg <= V0_trigger;
		end if;
	end process;
	
	process(clk160, reset, V0_reg, clk_ro_en)
	begin
	   if reset = '1' then
		   V0_signal(0) <= '0';
		elsif clk160'event and clk160 = '1' and clk_ro_en = '1' then
		   V0_signal(0) <= V0_reg;
		end if;
	end process;
	V0_parallized <= V0_signal;
	
		-- paralizer for V1 trigger assuming MSB logic
	process(clk160, reset, V1_trigger)
	begin
	   if reset = '1' then
		   V1_signal(1) <= '0';
		elsif clk160'event and clk160 = '1' and clk_ro_en = '1' then
		   V1_signal(1) <= V1_trigger;
		end if;
	end process;
	
	process(clk160, reset, V1_trigger)
	begin
	   if reset = '1' then
		   V1_reg <= '0';
		elsif clk160'event and clk160 = '1' then
		   V1_reg <= V1_trigger;
		end if;
	end process;
	
	process(clk160, reset, V1_reg, clk_ro_en)
	begin
	   if reset = '1' then
		   V1_signal(0) <= '0';
		elsif clk160'event and clk160 = '1' and clk_ro_en = '1' then
		   V1_signal(0) <= V1_reg;
		end if;
	end process;
	V1_parallized <= V1_signal;
	
		-- paralizer for V2 trigger assuming MSB logic
	process(clk160, reset, V2_trigger)
	begin
	   if reset = '1' then
		   V2_signal(1) <= '0';
		elsif clk160'event and clk160 = '1' and clk_ro_en = '1' then
		   V2_signal(1) <= V2_trigger;
		end if;
	end process;
	
	process(clk160, reset, V2_trigger)
	begin
	   if reset = '1' then
		   V2_reg <= '0';
		elsif clk160'event and clk160 = '1' then
		   V2_reg <= V2_trigger;
		end if;
	end process;
	
	process(clk160, reset, V2_reg, clk_ro_en)
	begin
	   if reset = '1' then
		   V2_signal(0) <= '0';
		elsif clk160'event and clk160 = '1' and clk_ro_en = '1' then
		   V2_signal(0) <= V2_reg;
		end if;
	end process;
	V2_parallized <= V2_signal;
	
		-- paralizer for V3 trigger assuming MSB logic
	process(clk160, reset, V3_trigger)
	begin
	   if reset = '1' then
		   V3_signal(1) <= '0';
		elsif clk160'event and clk160 = '1' and clk_ro_en = '1' then
		   V3_signal(1) <= V3_trigger;
		end if;
	end process;
	
	process(clk160, reset, V3_trigger)
	begin
	   if reset = '1' then
		   V3_reg <= '0';
		elsif clk160'event and clk160 = '1' then
		   V3_reg <= V3_trigger;
		end if;
	end process;
	
	process(clk160, reset, V3_reg, clk_ro_en)
	begin
	   if reset = '1' then
		   V3_signal(0) <= '0';
		elsif clk160'event and clk160 = '1' and clk_ro_en = '1' then
		   V3_signal(0) <= V3_reg;
		end if;
	end process;
   V3_parallized <= V3_signal;
	
	RAMB16_S4_S4_inst : RAMB16_S4_S4
   generic map (
      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
      -- The following INIT_xx declarations specify the initial contents of the RAM
      -- Address 0 to 1023
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 1024 to 2047
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 2048 to 3071
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 3072 to 4095
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
   port map (
      DOA => trigger_signal(3 downto 0),      -- Port A 4-bit Data Output
      DOB => LUT_data_out(3 downto 0),      -- Port B 2-bit Data Output
      --ADDRA => "000000000000",
		ADDRA(1 downto 0) => T0_signal(1 downto 0),  -- Port A 13-bit Address Input
		ADDRA(3 downto 2) => V0_signal(1 downto 0),
		ADDRA(5 downto 4)=> V1_signal(1 downto 0),
		ADDRA(7 downto 6)=> V2_signal(1 downto 0),
		ADDRA(9 downto 8)=> V3_signal(1 downto 0),
		ADDRA(11 downto 10) => "00",
      ADDRB => LUT_address(11 downto 0),  -- Port B 12-bit Address Input
      CLKA => clk160,    -- Port A Clock
      CLKB => clk120,    -- Port B Clock
      DIA => "0000",      -- Port A 4-bit Data Input
      DIB => LUT_data_in(3 downto 0),      -- Port B 4-bit Data Input
      ENA => '1',      -- Port A RAM Enable Input
      ENB => '1',      -- Port B RAM Enable Input
      SSRA => '0',    -- Port A Synchronous Set/Reset Input
      SSRB => '0',    -- Port B Synchronous Set/Reset Input
      WEA => '0',      -- Port A Write Enable Input
      WEB => LUT_we       -- Port B Write Enable Input
   );
	
trigger <= trigger_signal;

end Behavioral;