---------------------------------------------------------------------------------- -- Company: -- Engineer: Stefan Zimmer -- -- Create Date: 01:17:34 02/07/2008 -- Design Name: -- Module Name: CBTOFHANS_design - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: This box combines the trigger decisions from the five FEB boxes of one side -- to one trigger decision. This is done by parallizing the input from the FEB boxes. The two bits from -- each FEB box is given to the address input of a memory. The content of the memory (LUT), up to 4 Bit, is -- beeing send to the Central Control Box (CCB). It has also the cabability -- to adjust the timing of the different FEB_signals as well as the diagnosting tools like counters -- and an build in timing analyzer. -- In addition it manages the SCSN connection, neccessary for the communication with the FEB boxes. -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity CBCFPGA is port ( -- B_Channel : in std_logic; --S1_IN1 : in std_logic; --S1_IN2 : in std_logic; --S2_IN1 : in std_logic; --S2_IN2 : in std_logic; --S1_OUT1 : out std_logic; --S1_OUT2 : out std_logic; --S2_OUT1 : out std_logic; --S2_OUT2 : out std_logic; --CB_ : in std_logic; CB_C : in std_logic; CLK40n : in std_logic; CLK40p : in std_logic; CLK120n : in std_logic; CLK120p : in std_logic; SCSNFEBinn : in std_logic; SCSNFEBINp : in std_logic; SCSNFEBOUTn : out std_logic; SCSNFEBOUTp : out std_logic; SCSNINn : in std_logic; SCSNINp : in std_logic; SCSNOUTn : out std_logic; SCSNOUTp : out std_logic; -- TTC_Rdy : in std_logic; A_ECL : out std_logic; -- B_ECL : out std_logic; CB_TOF : out std_logic; LED1 : out std_logic; LED2 : out std_logic; L1ACCEPTp : in std_logic; -- ALL trigger signals from CTP come over this line L1ACCEPTn : in std_logic; PIMLINK0 : out std_logic; PIMLINK1 : out std_logic; --PIMLINK3 : out std_logic; L_OUTS : out std_logic; BUSY : in std_logic; SPA : out std_logic; SPB : out std_logic; SPC : in std_logic; SPD : in std_logic; CNRRL: out std_logic; --IO_C0 : out std_logic --IO_C1 : out std_logic; --IO_C2 : out std_logic; --IO_C3 : out std_logic; CLK40T: out std_logic; -- clk output to TOFFPGA CLK40_T0 : out std_logic; SCSNOUT_T0 : out std_logic; SELECTOR_T0 : out std_logic; KOINZ_T0 : in std_logic; CLK40_V0 : out std_logic; SCSNOUT_V0 : out std_logic; SELECTOR_V0 : out std_logic; KOINZ_V0 : in std_logic; CLK40_V1 : out std_logic ; SCSNOUT_V1 : out std_logic; SELECTOR_V1 : out std_logic; KOINZ_V1 : in std_logic; CLK40_V2 : out std_logic ; SCSNOUT_V2 : out std_logic; SELECTOR_V2 : out std_logic; KOINZ_V2 : in std_logic; CLK40_V3 : out std_logic; SCSNOUT_V3 : out std_logic; SELECTOR_V3 : out std_logic; KOINZ_V3 :in std_logic; T2 : out std_logic; T7 : out std_logic ); end CBCFPGA; architecture BEHAVIORAL of CBCFPGA is signal reset, reset_n : std_logic; signal CLK160 : std_logic; -- clk160 used in the design signal CLK120 : std_logic; signal clk120_pad : std_logic; -- direct signal from LVDS signal clk160_signal : std_logic; -- produced signal from DCM signal clk160_prebuf : std_logic; -- after sync DCM before clock network signal clk160_out_of_clk40 : std_logic; -- generate 160MHz clk signal clk40_from_clk160 : std_logic; -- phase conserved devided clk160 for locking signal CLK40 : std_logic; -- deskewed signal mainly used in the design signal clk80 : std_logic; signal clk40_postbuf : std_logic; signal clk40_pad: std_logic; -- direct signal from LVDS signal clk40_prebuf: std_logic; -- after DCM before clock network signal clk80_prebuf: std_logic; signal clk_en0deg, clk_en90deg, clk_en180deg, clk_en270deg: std_logic; signal clk_en0deg_prebuf, clk_en90deg_prebuf, clk_en180deg_prebuf, clk_en270deg_prebuf: std_logic; signal clk_scsn : std_logic; -- scsn bus signals signal SCSNFEBIN: std_logic; signal SCSNFEBOUT: std_logic; signal SCSNIN: std_logic; signal SCSNOUT: std_logic; signal scsn_data_buf: std_logic; signal scsn_addr_signal: std_logic_vector(15 downto 0); signal scsn_dataout_signal: std_logic_vector(31 downto 0); signal scsn_datain_signal: std_logic_vector(31 downto 0); signal scsn_bus_req_signal: std_logic; signal scsn_we_signal: std_logic; signal scsn_bus_ack_signal: std_logic; signal scsn_out_signal: std_logic; signal scsn_out_signal_i: std_logic; signal scsn_in_signal: std_logic; -- trigger signals signal scintillator_trigger_flash_signal: std_logic; signal L1ACCEPT : std_logic; signal LUT_trigger_signal : std_logic_vector(3 downto 0); signal LUT_trigger : std_logic_vector(3 downto 0); signal selected_trigger_signal, selected_trigger_signal_reg : std_logic_vector(3 downto 0); signal encoded_signal : std_logic; signal T0_parallized : std_logic_vector(1 downto 0); signal V0_parallized, V1_parallized, V2_parallized, V3_parallized : std_logic_vector(1 downto 0); signal KOINZ_signal : std_logic_vector(5 downto 1); signal FEB_KOINZ_signal : std_logic_vector(5 downto 1); -- Data signals signal pattern_sync_edge_rate_T0_signal: std_logic_vector(15 downto 0); signal pattern_sync_edge_rate_V0_signal: std_logic_vector(15 downto 0); signal pattern_sync_edge_rate_V1_signal: std_logic_vector(15 downto 0); signal pattern_sync_edge_rate_V2_signal: std_logic_vector(15 downto 0); signal pattern_sync_edge_rate_V3_signal: std_logic_vector(15 downto 0); signal T0_sync_signal : std_logic; signal V0_sync_signal : std_logic; signal V1_sync_signal : std_logic; signal V2_sync_signal : std_logic; signal V3_sync_signal : std_logic; signal LUT_data_in_signal : std_logic_vector(3 downto 0); signal LUT_address_signal : std_logic_vector(11 downto 0); signal LUT_we_signal : std_logic; signal LUT_data_out_signal: std_logic_vector(3 downto 0); type analyzer_std_logic is array(0 to 24) of std_logic; signal analyzer_sig1: analyzer_std_logic; type analyzer_sig0_type is array(0 to 24) of std_logic_vector(1 downto 0); signal analyzer_sig0: analyzer_sig0_type; signal analyzer_counter_en : std_logic_vector(24 downto 1); signal counter_reset : std_logic; signal FEB_reset_signal : std_logic_vector(5 downto 1); signal FEB_select_signal : std_logic_vector(5 downto 1); signal FEB_SCSNIN_combined_signal : std_logic_vector(5 downto 1); signal FEB_emulator_signal : std_logic_vector(5 downto 1); signal FEB_emulator_rising_edge_marker : std_logic; signal FEB_SCSNIN_signal : std_logic_vector(5 downto 1); signal KOINZ_input_mode_signal : std_logic_vector(5 downto 1); -- scsn configuration registers signal clk40_shift_reg_signal: std_logic_vector(1 downto 0); signal pattern_sync_edge_sel_T0_reg_signal: std_logic; signal pattern_sync_set_delay_T0_reg_signal: std_logic_vector(4 downto 0); signal pattern_sync_edge_sel_V0_reg_signal: std_logic; signal pattern_sync_set_delay_V0_reg_signal: std_logic_vector(4 downto 0); signal pattern_sync_edge_sel_V1_reg_signal: std_logic; signal pattern_sync_set_delay_V1_reg_signal: std_logic_vector(4 downto 0); signal pattern_sync_edge_sel_V2_reg_signal: std_logic; signal pattern_sync_set_delay_V2_reg_signal: std_logic_vector(4 downto 0); signal pattern_sync_edge_sel_V3_reg_signal: std_logic; signal pattern_sync_set_delay_V3_reg_signal: std_logic_vector(4 downto 0); signal T0_trigger_delay_reg_signal : std_logic_vector(4 downto 0); signal V0_trigger_delay_reg_signal : std_logic_vector(4 downto 0); signal V1_trigger_delay_reg_signal : std_logic_vector(4 downto 0); signal V2_trigger_delay_reg_signal : std_logic_vector(4 downto 0); signal V3_trigger_delay_reg_signal : std_logic_vector(4 downto 0); signal select_FEB_to_configure_reg_signal : std_logic_vector(2 downto 0); signal FEB_reset_reg_signal : std_logic_vector(5 downto 1); type type_FEB_disable_input_reg_signal is array(1 to 5) of std_logic; signal FEB_disable_input_reg_signal : type_FEB_disable_input_reg_signal; signal fiber_output_pattern_reg_signal: std_logic_vector(3 downto 0); signal fiber_output_pattern_en_reg_signal : std_logic; type std_logic_vec_array_1 is array(0 to 24) of std_logic_vector(2 downto 0); signal analyzer_pattern_sel_input_reg_signal : std_logic_vec_array_1; type std_logic_vec_array_2 is array(0 to 24) of std_logic_vector(1 downto 0); signal analyzer_pattern_in_reg_signal : std_logic_vec_array_2; type std_logic_vec_array_3 is array(0 to 24) of std_logic_vector(3 downto 0); signal analyzer_pattern_out_reg_signal : std_logic_vec_array_3; signal analyzer_pattern_coinz_en_reg_signal : analyzer_std_logic; signal counter_readout_req_reg_signal : std_logic; signal counter_reset_reg_signal : std_logic; -- monitoring signal signal counter_value_signal: std_logic_vector(47 downto 0); signal LUT_monitoring_Signal: std_logic_vector(31 downto 0); signal LUT_monitoring_coinz_signal: std_logic_vector(15 downto 0); signal counter_readout_done_signal: std_logic; signal readout_counter_addr_signal: std_logic_vector(5 downto 0); signal zero_signal: std_logic_vector(63 downto 0) := X"0000000000000000"; signal T0_parallized_signal: std_logic_vector(1 downto 0); signal V0_parallized_signal: std_logic_vector(1 downto 0); signal V1_parallized_signal: std_logic_vector(1 downto 0); signal V2_parallized_signal: std_logic_vector(1 downto 0); signal V3_parallized_signal: std_logic_vector(1 downto 0); signal T0_coinzidence_signal: std_logic; signal V0_coinzidence_signal: std_logic; signal V1_coinzidence_signal: std_logic; signal V2_coinzidence_signal: std_logic; signal V3_coinzidence_signal: std_logic; signal co_sig: std_logic_vector(4 downto 0); -- timing analyzer signals signal done_timing_analyze_signal: std_logic; signal clear_timing_analyze_reg_signal: std_logic; signal activate_timing_analyze_reg_signal: std_logic; signal timing_analyze_trigger_pattern_reg_signal: std_logic_vector(31 downto 0); signal readout_address_data_analyze_signal: std_logic_vector(8 downto 0); signal readout_value_data_analyze_signal: std_logic_vector(31 downto 0); signal readout_value_data_analyze_signal_reg: std_logic_vector(31 downto 0); -- cabling signal q : std_logic_vector(7 downto 0); -- test and debug signal ds_count : std_logic_vector(15 downto 0); signal cbtof_src : std_logic_vector(2 downto 0); signal spare_src : std_logic_vector(2 downto 0); signal spare : std_logic; signal CB_TOF_sig : std_logic; signal CB_C_sync : std_logic; signal test_d1 : std_logic_vector(15 downto 0); component IBUFDS port (I : in STD_LOGIC; IB : in STD_LOGIC; O : out STD_LOGIC); end component; component OBUFDS port (I : in STD_LOGIC; O : out STD_LOGIC; OB : out STD_LOGIC); end component; COMPONENT clk_enable_logic PORT( clk160 : IN std_logic; reset : IN std_logic; clk40 : IN std_logic; select_offset : in STD_LOGIC_vector(1 downto 0); en0deg : OUT std_logic; en90deg : OUT std_logic; en180deg : OUT std_logic; en270deg : OUT std_logic ); END COMPONENT; COMPONENT mcm_network_interface PORT( ser0_din : IN std_logic; ser1_din : IN std_logic; bus_din : IN std_logic_vector(31 downto 0); bus_ack : IN std_logic; reset_n : IN std_logic; clk_buf : IN std_logic; clk : IN std_logic; ser0_dout : OUT std_logic; ser1_dout : OUT std_logic; bus_addr : OUT std_logic_vector(15 downto 0); bus_dout : OUT std_logic_vector(31 downto 0); bus_req : OUT std_logic; bus_we : OUT std_logic; chipRST_n : OUT std_logic; clk_buf_disable : OUT std_logic ); END COMPONENT; COMPONENT Counter_64times48Bit PORT( counter_en : IN std_logic_vector(62 downto 0); clk : IN std_logic; clk160 : IN std_logic; clk_scsn : IN std_logic; readout_req : IN std_logic; reset : IN std_logic; readout_counter_addr : IN std_logic_vector(5 downto 0); readout_done : OUT std_logic; counter_value : OUT std_logic_vector(47 downto 0); debug_signal : OUT std_logic_vector(7 downto 0) ); END COMPONENT; COMPONENT timing_analyze_module PORT( activate : IN std_logic; reset : IN std_logic; clear : IN std_logic; signals : IN std_logic_vector(31 downto 0); clk : IN std_logic; clk_scsn : IN std_logic; readout_address : IN std_logic_vector(8 downto 0); done : OUT std_logic; readout_value : OUT std_logic_vector(31 downto 0); trigger_mask : IN std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT trigger_flash PORT( puls : IN std_logic; clk : IN std_logic; reset : IN std_logic; flash : OUT std_logic ); END COMPONENT; COMPONENT LUT_emulation PORT( clk40 : IN std_logic; reset : IN std_logic; LUT_data_out : OUT std_logic_vector(3 downto 0) ); END COMPONENT; COMPONENT fiber_encode PORT( clk40 : IN std_logic; clk160 : IN std_logic; LUT_data : IN std_logic_vector(3 downto 0); encoded_signal : OUT std_logic; clk_en_first_bit_marker : in std_logic; reset : in std_logic ); END COMPONENT; COMPONENT pattern_sync PORT( reset : IN std_logic; clk160 : IN std_logic; signal_in : IN std_logic; edge_sel : IN std_logic; set_delay : IN std_logic_vector(4 downto 0); signal_sync_delayed : OUT std_logic; edge_rate : OUT std_logic_vector(15 downto 0) ); END COMPONENT; COMPONENT FEB_emulator PORT( clk160 : IN std_logic; clk80 : IN std_logic; clk40 : IN std_logic; reset : IN std_logic; pattern1 : IN std_logic_vector(1 downto 0); pattern2 : IN std_logic_vector(1 downto 0); pat1_per_pat2 : IN std_logic_vector(15 downto 0); enable : IN std_logic; output : OUT std_logic; rising_edge_marker_reg : in std_logic ); END COMPONENT; COMPONENT LUT_module_CBC PORT( T0_trigger : IN std_logic; V0_trigger : IN std_logic; V1_trigger : IN std_logic; V2_trigger : IN std_logic; V3_trigger : IN std_logic; clk160 : IN std_logic; clk120 : IN std_logic; clk_ro_en_minus180_reg : IN std_logic; clk_ro_en_reg : IN std_logic; reset : IN std_logic; LUT_address : IN std_logic_vector(11 downto 0); LUT_data_in : IN std_logic_vector(3 downto 0); LUT_we : IN std_logic; trigger : OUT std_logic_vector(3 downto 0); LUT_data_out : OUT std_logic_vector(3 downto 0); T0_parallized : OUT std_logic_vector(1 downto 0); V0_parallized : OUT std_logic_vector(1 downto 0); V1_parallized : OUT std_logic_vector(1 downto 0); V2_parallized : OUT std_logic_vector(1 downto 0); V3_parallized : OUT std_logic_vector(1 downto 0) ); END COMPONENT; signal SCSNIN_signal: std_logic; signal SCSNOUT_signal: std_logic; begin IBUFDS_CLK120: IBUFDS port map ( O => CLK120_pad, I => CLK120p, IB => CLK120n ); IBUFDS_CLK40: IBUFDS port map ( O => CLK40_pad, -- uncomment for developing in HD clock comes from cbtof via fiber to the busy input --O => open, I => CLK40p, IB => CLK40n ); --clk40_pad <= CB_C; -- for developing in HD clock comes from cbtof via fiber to the busy input --clk40_pad <= S1_IN1; IBUFDS_L1ACCEPT: IBUFDS port map ( O => L1ACCEPT, I => L1ACCEPTp, IB => L1ACCEPTn ); IBUFDS_SCSNFEBIN: IBUFDS port map ( O => SCSNFEBIN, I => SCSNFEBINp, IB => SCSNFEBINn ); OBUFDS_SCSNFEBOUT: OBUFDS port map ( I => SCSNFEBOUT, O => SCSNFEBOUTp, OB => SCSNFEBOUTn ); IBUFDS_SCSNIN: IBUFDS port map ( O => SCSNIN, I => SCSNINp, IB => SCSNINn ); OBUFDS_SCSNOUT: OBUFDS port map ( I => SCSNOUT, O => SCSNOUTp, OB => SCSNOUTn ); -- deskew clk40 DCM_SP_inst1 : DCM_SP generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 25.0, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X" DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for -- frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE port map ( CLK0 => clk40_prebuf, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => clk80_prebuf, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => open, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clk40, -- DCM clock feedback CLKIN => clk40_pad, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => open, -- Dynamic phase adjust clock input PSEN => open, -- Dynamic phase adjust enable input PSINCDEC => open, -- Dynamic phase adjust increment/decrement RST => open -- DCM asynchronous reset input ); BUFG_inst_clk40 : BUFG port map ( O => clk40, -- Clock buffer output I => clk40_prebuf -- Clock buffer input ); BUFG_inst_clk_scsn : BUFG port map ( O => clk_scsn, -- Clock buffer output I => clk40_prebuf -- Clock buffer input ); BUFG_inst_clk80 : BUFG port map ( O => clk80, -- Clock buffer output I => clk80_prebuf -- Clock buffer input ); -- clk120 deskew DCM_SP_inst2 : DCM_SP generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 8.0, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X" DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "HIGH", -- "HIGH" or "LOW" frequency mode for -- frequency synthesis DLL_FREQUENCY_MODE => "HIGH", -- "HIGH" or "LOW" frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE port map ( CLK0 => clk120, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => LED1, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clk120, -- DCM clock feedback CLKIN => clk120_pad, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => open, -- Dynamic phase adjust clock input PSEN => open, -- Dynamic phase adjust enable input PSINCDEC => open, -- Dynamic phase adjust increment/decrement RST => open -- DCM asynchronous reset input ); -- produce and deskew clk160 DCM_SP_inst3 : DCM_SP generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 12.5, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" CLK_FEEDBACK => "2X", -- Specify clock feedback of "NONE", "1X" or "2X" DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for -- frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE port map ( CLK0 => open, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => clk160_prebuf, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => open, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clk160, -- DCM clock feedback CLKIN => clk80, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => open, -- Dynamic phase adjust clock input PSEN => open, -- Dynamic phase adjust enable input PSINCDEC => open, -- Dynamic phase adjust increment/decrement RST => open -- DCM asynchronous reset input ); BUFG_inst_clk160 : BUFG port map ( O => clk160, -- Clock buffer output I => clk160_prebuf -- Clock buffer input ); Inst_mcm_network_interface: mcm_network_interface PORT MAP( ser0_din => SCSNIN_signal, ser0_dout => SCSNOUT_signal, ser1_din => '0', ser1_dout => open , bus_addr => scsn_addr_signal, bus_dout => scsn_dataout_signal, bus_din => scsn_datain_signal, bus_req => scsn_bus_req_signal, bus_we => scsn_we_signal, bus_ack => scsn_bus_ack_signal, chipRST_n => reset_n, reset_n => '1', clk_buf_disable => open, -- to save power, the clk can be switched off clk_buf => CLK_SCSN, -- the clock which can be switched off clk => CLK_SCSN ); process(clk40, reset, scsn_bus_req_signal) begin if (reset='1') then scsn_bus_ack_signal <= '0'; elsif (clk40'event and clk40 = '1') then scsn_bus_ack_signal <= scsn_bus_req_signal; end if; end process; Inst_clk_enable_logic: clk_enable_logic PORT MAP( clk160 => clk160, reset => reset, clk40 => clk40, select_offset => clk40_shift_reg_signal, en0deg => clk_en0deg_prebuf, en90deg => clk_en90deg_prebuf, en180deg => clk_en180deg_prebuf, en270deg => clk_en270deg ); BUFG_inst_clk_en0deg : BUFG port map ( O => clk_en0deg, -- Clock buffer output I => clk_en0deg_prebuf -- Clock buffer input ); BUFG_inst_clk_en90deg : BUFG port map ( O => clk_en90deg, -- Clock buffer output I => clk_en90deg_prebuf -- Clock buffer input ); BUFG_inst_clk_en180deg : BUFG port map ( O => clk_en180deg, -- Clock buffer output I => clk_en180deg_prebuf -- Clock buffer input ); -- clock counter process(clk160, reset , q) begin if reset = '1' then q <= X"00"; elsif clk160'event and clk160 = '1' then q <= q + '1'; end if; end process; process(scsn_we_signal, scsn_dataout_signal, scsn_addr_signal, counter_value_signal) begin -- some dummy readout for testing scsn communication if (scsn_addr_signal = 0) then scsn_datain_signal <= X"deadface"; elsif (scsn_addr_signal = 2) then scsn_datain_signal <=X"0000face"; elsif (scsn_addr_signal = 350) then scsn_datain_signal(0) <= pattern_sync_edge_sel_T0_reg_signal; scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 351) then scsn_datain_signal(4 downto 0) <= pattern_sync_set_delay_T0_reg_signal; scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 352) then scsn_datain_signal(15 downto 0) <= pattern_sync_edge_rate_T0_signal(15 downto 0); scsn_datain_signal(31 downto 16) <= zero_signal(31 downto 16); elsif (scsn_addr_signal = 353) then scsn_datain_signal(0) <= FEB_disable_input_reg_signal(5); scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 310) then scsn_datain_signal(0) <= pattern_sync_edge_sel_V0_reg_signal; scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 311) then scsn_datain_signal(4 downto 0) <= pattern_sync_set_delay_V0_reg_signal; scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 312) then scsn_datain_signal(15 downto 0) <= pattern_sync_edge_rate_V0_signal(15 downto 0); scsn_datain_signal(31 downto 16) <= zero_signal(31 downto 16); elsif (scsn_addr_signal = 313) then scsn_datain_signal(0) <= FEB_disable_input_reg_signal(1); scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 320) then scsn_datain_signal(0) <= pattern_sync_edge_sel_V1_reg_signal; scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 321) then scsn_datain_signal(4 downto 0) <= pattern_sync_set_delay_V1_reg_signal; scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 322) then scsn_datain_signal(15 downto 0) <= pattern_sync_edge_rate_V1_signal(15 downto 0); scsn_datain_signal(31 downto 16) <= zero_signal(31 downto 16); elsif (scsn_addr_signal = 323) then scsn_datain_signal(0) <= FEB_disable_input_reg_signal(2); scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 330) then scsn_datain_signal(0) <= pattern_sync_edge_sel_V2_reg_signal; scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 331) then scsn_datain_signal(4 downto 0) <= pattern_sync_set_delay_V2_reg_signal; scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 332) then scsn_datain_signal(15 downto 0) <= pattern_sync_edge_rate_V2_signal(15 downto 0); scsn_datain_signal(31 downto 16) <= zero_signal(31 downto 16); elsif (scsn_addr_signal = 333) then scsn_datain_signal(0) <= FEB_disable_input_reg_signal(3); scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 340) then scsn_datain_signal(0) <= pattern_sync_edge_sel_V3_reg_signal; scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 341) then scsn_datain_signal(4 downto 0) <= pattern_sync_set_delay_V3_reg_signal; scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 342) then scsn_datain_signal(15 downto 0) <= pattern_sync_edge_rate_V3_signal(15 downto 0); scsn_datain_signal(31 downto 16) <= zero_signal(31 downto 16); elsif (scsn_addr_signal = 343) then scsn_datain_signal(0) <= FEB_disable_input_reg_signal(4); scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); -- fiber output pattern mode elsif (scsn_addr_signal = 360) then scsn_datain_signal(0) <= fiber_output_pattern_en_reg_signal; scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); -- fiber output pattern elsif (scsn_addr_signal = 361) then scsn_datain_signal(3 downto 0) <= fiber_output_pattern_reg_signal; scsn_datain_signal(31 downto 4) <= zero_signal(31 downto 4); -- clear timing analyzer elsif (scsn_addr_signal = 600) then scsn_datain_signal(0) <= clear_timing_analyze_reg_signal; scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); -- set trigger pattern elsif (scsn_addr_signal = 601) then scsn_datain_signal <= timing_analyze_trigger_pattern_reg_signal; -- active timing analyze elsif (scsn_addr_signal = 602) then scsn_datain_signal(0) <= activate_timing_analyze_reg_signal; scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); -- counter reset elsif (scsn_addr_signal = 50) then scsn_datain_signal(0) <= counter_reset_reg_signal; scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); -- counter readout req elsif (scsn_addr_signal = 51) then scsn_datain_signal(0) <= counter_readout_req_reg_signal; scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); -- select FEB to configure elsif (scsn_addr_signal = 999) then scsn_datain_signal(2 downto 0) <= select_feb_to_configure_reg_signal; scsn_datain_signal(31 downto 3) <= zero_signal(31 downto 3); -- FEB reset elsif (scsn_addr_signal = 410) then scsn_datain_signal(0) <= FEB_reset_reg_signal(1); scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 420) then scsn_datain_signal(0) <= FEB_reset_reg_signal(2); scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 430) then scsn_datain_signal(0) <= FEB_reset_reg_signal(3); scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 440) then scsn_datain_signal(0) <= FEB_reset_reg_signal(4); scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 450) then scsn_datain_signal(0) <= FEB_reset_reg_signal(5); scsn_datain_signal(31 downto 30) <= zero_signal(31 downto 30); elsif (scsn_addr_signal = 90) then scsn_datain_signal(2 downto 0) <= cbtof_src; scsn_datain_signal(31 downto 3) <= zero_signal(31 downto 3); elsif (scsn_addr_signal = 91) then scsn_datain_signal(2 downto 0) <= spare_src; scsn_datain_signal(31 downto 3) <= zero_signal(31 downto 3); elsif (scsn_addr_signal = 92) then scsn_datain_signal(0) <= CB_C_sync; scsn_datain_signal(31 downto 1) <= zero_signal(31 downto 1); elsif (scsn_addr_signal = 52) then scsn_datain_signal(0) <= counter_readout_done_signal; scsn_datain_signal(31 downto 1) <= zero_signal(31 downto 1); -- addresses starting with 1xxxxxxxxxxxxxxx = 65536 are for the LUT elsif (scsn_addr_signal(15) = '1' )then scsn_datain_signal(3 downto 0) <= LUT_data_out_signal(3 downto 0); scsn_datain_signal(31 downto 4) <= zero_signal(31 downto 4); -- read out counter -- for bit 31 downto 0 use 64xx -- for bit 47 downto 32 use 128xx -- check if readout is allready done -- read counter values elsif (scsn_addr_signal(15 downto 6) = "0001100100") then scsn_datain_signal(31 downto 0) <= counter_value_signal(31 downto 0); elsif (scsn_addr_signal(15 downto 6) = "0011001000") then scsn_datain_signal(15 downto 0) <= counter_value_signal(47 downto 32); scsn_datain_signal(31 downto 16) <= zero_signal(31 downto 16); -- timing analyze data elsif (scsn_addr_signal = 603) then scsn_datain_signal(0) <= done_timing_analyze_signal; scsn_datain_signal(31 downto 1) <= zero_signal(31 downto 1); -- addresses 16384 ... 16895 for the timing analyzer elsif (scsn_addr_signal(15 downto 14) = "01") then scsn_datain_signal(31 downto 0) <= readout_value_data_analyze_signal_reg(31 downto 0); else scsn_datain_signal(31 downto 0) <= zero_signal(31 downto 0); end if; end process; SCSNIN_signal<=SCSNIN; SCSNOUT <= SCSNOUT_signal; -- ############################################################# -- ######### configuration ##################################### -- ############################################################# process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then clk40_shift_reg_signal(1 downto 0) <= "00"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 99) then clk40_shift_reg_signal(1 downto 0) <= scsn_dataout_signal(1 downto 0); end if; end process; -- syncronizer for the FEB signals -- syncronizer T0 process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pattern_sync_edge_sel_T0_reg_signal<= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 350) then pattern_sync_edge_sel_T0_reg_signal <= scsn_dataout_signal(0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pattern_sync_set_delay_T0_reg_signal <= "00000"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 351) then pattern_sync_set_delay_T0_reg_signal <= scsn_dataout_signal(4 downto 0); end if; end process; -- syncronizer V0 process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pattern_sync_edge_sel_V0_reg_signal<= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 310) then pattern_sync_edge_sel_V0_reg_signal <= scsn_dataout_signal(0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pattern_sync_set_delay_V0_reg_signal <= "00000"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 311) then pattern_sync_set_delay_V0_reg_signal <= scsn_dataout_signal(4 downto 0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pattern_sync_edge_sel_V1_reg_signal<= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 320) then pattern_sync_edge_sel_V1_reg_signal <= scsn_dataout_signal(0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pattern_sync_set_delay_V1_reg_signal <= "00000"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 321) then pattern_sync_set_delay_V1_reg_signal <= scsn_dataout_signal(4 downto 0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pattern_sync_edge_sel_V2_reg_signal<= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 330) then pattern_sync_edge_sel_V2_reg_signal <= scsn_dataout_signal(0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pattern_sync_set_delay_V2_reg_signal <= "00000"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 331) then pattern_sync_set_delay_V2_reg_signal <= scsn_dataout_signal(4 downto 0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pattern_sync_edge_sel_V3_reg_signal<= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 340) then pattern_sync_edge_sel_V3_reg_signal <= scsn_dataout_signal(0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pattern_sync_set_delay_V3_reg_signal <= "00000"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 341) then pattern_sync_set_delay_V3_reg_signal <= scsn_dataout_signal(4 downto 0); end if; end process; -- LUT configuration -- all addresses starting with "1000" & X"0000000" are reserved for the LUT -- be careful not all address bits are used so fare, due to hardware limitations LUT_data_in_signal(3 downto 0) <= scsn_dataout_signal(3 downto 0); LUT_address_signal(11 downto 0) <= scsn_addr_signal(11 downto 0); LUT_we_signal <='1' when (scsn_addr_signal(15) = '1' and scsn_we_signal = '1') else '0'; -- select FEB modes 0 = trigger/ reset mode; 1 = configuration; -- reset signals for FEBs process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then select_feb_to_configure_reg_signal <= "000"; -- 0 the default mode all FEBs are in trigger mode elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 999) then select_feb_to_configure_reg_signal <= scsn_dataout_signal(2 downto 0); end if; end process; FEB_resets: for ii in 1 to 5 generate process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then FEB_reset_reg_signal(ii) <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 400 + (ii*10)) then FEB_reset_reg_signal(ii) <= scsn_dataout_signal(0); end if; end process; end generate; -- switch FEB inputs between real input and pattern_gen/off if pattern_gen is disabled pattern_gen_configuration: for ii in 1 to 5 generate process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then FEB_disable_input_reg_signal(ii) <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 303 + 10*ii) then FEB_disable_input_reg_signal(ii) <= scsn_dataout_signal(0); end if; end process; end generate; -- fiber output generator process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then fiber_output_pattern_en_reg_signal <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 360) then fiber_output_pattern_en_reg_signal <= scsn_dataout_signal(0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then fiber_output_pattern_reg_signal <= "0000"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 361) then fiber_output_pattern_reg_signal <= scsn_dataout_signal(3 downto 0); end if; end process; -- analyzer configuration register_for_analyzer: for ii in 0 to 24 generate begin process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then analyzer_pattern_sel_input_reg_signal(ii) <= "000"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 500 + (10*ii)) then analyzer_pattern_sel_input_reg_signal(ii) <= scsn_dataout_signal(2 downto 0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then analyzer_pattern_in_reg_signal(ii) <= "00"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 501 + (10*ii)) then analyzer_pattern_in_reg_signal(ii) <= scsn_dataout_signal(1 downto 0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then analyzer_pattern_out_reg_signal(ii) <= "0000"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 502 + (10*ii)) then analyzer_pattern_out_reg_signal(ii) <= scsn_dataout_signal(3 downto 0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then analyzer_pattern_coinz_en_reg_signal(ii) <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 503 + (10*ii)) then analyzer_pattern_coinz_en_reg_signal(ii) <= scsn_dataout_signal(0); end if; end process; end generate; -- timing analyzer -- activate timing analyze module process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then activate_timing_analyze_reg_signal <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 602) then activate_timing_analyze_reg_signal <= scsn_dataout_signal(0); end if; end process; -- clear timing analyze module (make it ready for the next activate) process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then clear_timing_analyze_reg_signal <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 600) then clear_timing_analyze_reg_signal <= scsn_dataout_signal(0); end if; end process; -- set trigger pattern for timing analyze module process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal(31 downto 0), scsn_addr_signal) begin if (reset = '1') then timing_analyze_trigger_pattern_reg_signal(31 downto 0) <= X"00000000"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 601) then timing_analyze_trigger_pattern_reg_signal(31 downto 0) <= scsn_dataout_signal(31 downto 0); end if; end process; -- counter controll -- Counter process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then counter_reset_reg_signal <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 50) then counter_reset_reg_signal <= scsn_dataout_signal(0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then counter_readout_req_reg_signal <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 51) then counter_readout_req_reg_signal <= scsn_dataout_signal(0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then cbtof_src <= ( others => '0'); elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 90) then cbtof_src <= scsn_dataout_signal(2 downto 0); end if; end process; process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then spare_src <= ( others => '0'); elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 91) then spare_src <= scsn_dataout_signal(2 downto 0); end if; end process; --################################################################# --########### communication with other pretrigger parts ########## --################################################################# -- the CB-Logic gets an reset from the SCSN bus reset <= not reset_n; -- select and operate the FEB mode (configuration or trigger) sel_FEB_mode: for ii in 1 to 5 generate begin -- -- only accept the FEB reset signal in trigger mode, switch to pattern mode instead -- KOINZ_input_mode_signal(ii) <= FEB_disable_input_reg_signal(ii) or FEB_select_signal(ii); FEB_reset_signal(ii) <= (not FEB_select_signal(ii)) and FEB_reset_reg_signal(ii); -- FEB_SCSNIN line can be FEB reset (trigger mode) or SCSN input to FEBs (config mode) FEB_SCSNIN_combined_signal(ii) <= FEB_reset_signal(ii) or FEB_SCSNIN_signal(ii); -- use the KOINZ signal as trigger signal (trigger mode) or as SCSN backchannel (config mode) --KOINZ_signal(ii) <= FEB_emulator_signal(ii) when KOINZ_input_mode_signal(ii) = '1' else FEB_KOINZ_signal(ii); KOINZ_signal(ii) <= FEB_KOINZ_signal(ii) and (not FEB_disable_input_reg_signal(ii)); end generate; process(FEB_KOINZ_signal, SCSNFEBOUT, select_FEB_to_configure_reg_signal) begin -- MUX for FEB scsn output case select_FEB_to_configure_reg_signal is when "101" => SCSNFEBOUT <= FEB_KOINZ_signal(5); when "001" => SCSNFEBOUT <= FEB_KOINZ_signal(1); when "010" => SCSNFEBOUT <= FEB_KOINZ_signal(2); when "011" => SCSNFEBOUT <= FEB_KOINZ_signal(3); when "100" => SCSNFEBOUT <= FEB_KOINZ_signal(4); when others => SCSNFEBOUT <= '0'; end case; end process; -- MUXes for FEB SCSNOUTPUTS -- importent set the FEB_SCSNIN_signal to 0 in trigger mode since a 1 will reset the FEBs FEB_SCSNIN_signal(5) <= SCSNFEBIN when select_FEB_to_configure_reg_signal = "101" else '0'; FEB_SCSNIN_signal(1) <= SCSNFEBIN when select_FEB_to_configure_reg_signal = "001" else '0'; FEB_SCSNIN_signal(2) <= SCSNFEBIN when select_FEB_to_configure_reg_signal = "010" else '0'; FEB_SCSNIN_signal(3) <= SCSNFEBIN when select_FEB_to_configure_reg_signal = "011" else '0'; FEB_SCSNIN_signal(4) <= SCSNFEBIN when select_FEB_to_configure_reg_signal = "100" else '0'; -- MUXes for FEB select outputs FEB_Select_signal(5) <= '1' when select_FEB_to_configure_reg_signal = "101" else '0'; FEB_Select_signal(1) <= '1' when select_FEB_to_configure_reg_signal = "001" else '0'; FEB_Select_signal(2) <= '1' when select_FEB_to_configure_reg_signal = "010" else '0'; FEB_Select_signal(3) <= '1' when select_FEB_to_configure_reg_signal = "011" else '0'; FEB_Select_signal(4) <= '1' when select_FEB_to_configure_reg_signal = "100" else '0'; CLK40_T0 <= clk40; SCSNOUT_T0 <= FEB_SCSNIN_combined_signal(5); SELECTOR_T0 <= FEB_Select_signal(5); FEB_KOINZ_signal(5) <= KOINZ_T0; CLK40_V0 <= clk40; SCSNOUT_V0 <= FEB_SCSNIN_combined_signal(1); SELECTOR_V0 <= FEB_Select_signal(1); FEB_KOINZ_signal(1) <= KOINZ_V0; CLK40_V1 <= clk40; SCSNOUT_V1 <= FEB_SCSNIN_combined_signal(2); SELECTOR_V1 <= FEB_Select_signal(2); FEB_KOINZ_signal(2) <= KOINZ_V1; CLK40_V2 <= clk40; SCSNOUT_V2 <= FEB_SCSNIN_combined_signal(3); SELECTOR_V2 <= FEB_Select_signal(3); FEB_KOINZ_signal(3) <= KOINZ_V2; CLK40_V3 <= clk40; SCSNOUT_V3 <= FEB_SCSNIN_combined_signal(4); SELECTOR_V3 <= FEB_Select_signal(4); FEB_KOINZ_signal(4) <= KOINZ_V3; -- Syncronizer for FEBs Inst_pattern_sync_T0: pattern_sync PORT MAP( reset => reset, clk160 => clk160, signal_in => KOINZ_signal(5), edge_sel => pattern_sync_edge_sel_T0_reg_signal, signal_sync_delayed => T0_sync_signal, edge_rate(15 downto 0) => pattern_sync_edge_rate_T0_signal(15 downto 0), set_delay(4 downto 0) => pattern_sync_set_delay_T0_reg_signal(4 downto 0) ); Inst_pattern_sync_V0: pattern_sync PORT MAP( reset => reset, clk160 => clk160, signal_in => KOINZ_signal(1), edge_sel => pattern_sync_edge_sel_V0_reg_signal, signal_sync_delayed => V0_sync_signal, edge_rate(15 downto 0) => pattern_sync_edge_rate_V0_signal(15 downto 0), set_delay(4 downto 0) => pattern_sync_set_delay_V0_reg_signal(4 downto 0) ); Inst_pattern_sync_V1: pattern_sync PORT MAP( reset => reset, clk160 => clk160, signal_in => KOINZ_signal(2), edge_sel => pattern_sync_edge_sel_V1_reg_signal, signal_sync_delayed => V1_sync_signal, edge_rate(15 downto 0) => pattern_sync_edge_rate_V1_signal(15 downto 0), set_delay(4 downto 0) => pattern_sync_set_delay_V1_reg_signal(4 downto 0) ); Inst_pattern_sync_V2: pattern_sync PORT MAP( reset => reset, clk160 => clk160, signal_in => KOINZ_signal(3), edge_sel => pattern_sync_edge_sel_V2_reg_signal, signal_sync_delayed => V2_sync_signal, edge_rate(15 downto 0) => pattern_sync_edge_rate_V2_signal(15 downto 0), set_delay(4 downto 0) => pattern_sync_set_delay_V2_reg_signal(4 downto 0) ); Inst_pattern_sync_KOINZ_V3: pattern_sync PORT MAP( reset => reset, clk160 => clk160, signal_in => KOINZ_signal(4), edge_sel => pattern_sync_edge_sel_V3_reg_signal, signal_sync_delayed => V3_sync_signal, edge_rate(15 downto 0) => pattern_sync_edge_rate_V3_signal(15 downto 0), set_delay(4 downto 0) => pattern_sync_set_delay_V3_reg_signal(4 downto 0) ); Inst_pattern_sync_test: pattern_sync PORT MAP( reset => reset, clk160 => clk160, signal_in => CB_C, edge_sel => pattern_sync_edge_sel_V0_reg_signal, signal_sync_delayed => CB_C_sync, edge_rate(15 downto 0) => test_d1(15 downto 0), set_delay(4 downto 0) => pattern_sync_set_delay_V0_reg_signal(4 downto 0) ); -- ############################################################# -- ######### trigger processing ################################ -- ############################################################# Inst_LUT_module_CBC: LUT_module_CBC PORT MAP( T0_trigger => T0_sync_signal, V0_trigger => V0_sync_signal, V1_trigger => V1_sync_signal, V2_trigger => V2_sync_signal, V3_trigger => V3_sync_signal, trigger => LUT_trigger_signal, clk160 => clk160, clk120 => clk_scsn, clk_ro_en_reg => clk_en0deg, clk_ro_en_minus180_reg => clk_en180deg, reset => reset, LUT_address => LUT_address_signal, LUT_data_in => LUT_data_in_signal, LUT_we => LUT_we_signal, LUT_data_out => LUT_data_out_signal, T0_parallized => T0_parallized_signal, V0_parallized => V0_parallized_signal, V1_parallized => V1_parallized_signal, V2_parallized => V2_parallized_signal, V3_parallized => V3_parallized_signal ); -- LUT emulator: send in a certain period a triggerpattern --Inst_LUT_emulation: LUT_emulation PORT MAP( -- clk40 => clk40, -- reset => reset, -- LUT_data_out(3 downto 0) => LUT_data_out_signal(3 downto 0) --); Inst_trigger_flash: trigger_flash PORT MAP( puls => encoded_signal, clk => clk40, reset => reset, flash => open --LED1 ); -- ####################################################### -- ############# monitoring ############################## -- ####################################################### counter_reset <= counter_reset_reg_signal or reset; Inst_Counter_64times48Bit: Counter_64times48Bit PORT MAP( counter_en(0) => '1', counter_en(24 downto 1) => analyzer_counter_en(24 downto 1), counter_en(26 downto 25) => zero_signal(26 downto 25), counter_en(28 downto 27) => T0_parallized_signal(1 downto 0), counter_en(30 downto 29) => V0_parallized_signal(1 downto 0), counter_en(32 downto 31) => V1_parallized_signal(1 downto 0), counter_en(34 downto 33) => V2_parallized_signal(1 downto 0), counter_en(36 downto 35) => V3_parallized_signal(1 downto 0), counter_en(37) => T0_coinzidence_signal, counter_en(38) => V0_coinzidence_signal, counter_en(39) => V1_coinzidence_signal, counter_en(40) => V2_coinzidence_signal, counter_en(41) => V3_coinzidence_signal, counter_en(45 downto 42) => selected_trigger_signal(3 downto 0), -- the bits that go on the fiber counter_en(46) => CB_TOF_sig, counter_en(62 downto 47) => zero_signal(62 downto 47), clk => clk40, clk160 => clk160, clk_scsn => clk_scsn, readout_req => counter_readout_req_reg_signal, reset => counter_reset, readout_done => counter_readout_done_signal, readout_counter_addr => readout_counter_addr_signal(5 downto 0), counter_value(47 downto 0) => counter_value_signal(47 downto 0) ); -- address for counter readout readout_counter_addr_signal(5 downto 0) <= scsn_addr_signal(5 downto 0); -- T0 process(T0_sync_signal,clk160, reset) begin if reset = '1' then T0_parallized(0) <= T0_sync_signal; elsif clk160'event and clk160 = '1' then T0_parallized(0) <= T0_sync_signal; end if; end process; process(T0_parallized(0),clk160, reset) begin if reset = '1' then T0_parallized(1) <= T0_parallized(0); elsif clk160'event and clk160 = '1' then T0_parallized(1) <= T0_parallized(0); end if; end process; -- V0 process(V0_sync_signal,clk160, reset) begin if reset = '1' then V0_parallized(0) <= '0'; elsif clk160'event and clk160 = '1' then V0_parallized(0) <= V0_sync_signal; end if; end process; process(T0_parallized(0),clk160, reset) begin if reset = '1' then V0_parallized(1) <= V0_parallized(0); elsif clk160'event and clk160 = '1' then V0_parallized(1) <= V0_parallized(0); end if; end process; -- V1 process(V1_sync_signal,clk160, reset) begin if reset = '1' then V1_parallized(0) <= '0'; elsif clk160'event and clk160 = '1' then V1_parallized(0) <= V1_sync_signal; end if; end process; process(T0_parallized(0),clk160, reset) begin if reset = '1' then V1_parallized(1) <= V1_parallized(0); elsif clk160'event and clk160 = '1' then V1_parallized(1) <= V1_parallized(0); end if; end process; -- V2 process(V2_sync_signal,clk160, reset) begin if reset = '1' then V2_parallized(0) <= '0'; elsif clk160'event and clk160 = '1' then V2_parallized(0) <= V2_sync_signal; end if; end process; process(V2_parallized(0),clk160, reset) begin if reset = '1' then V2_parallized(1) <= '0'; elsif clk160'event and clk160 = '1' then V2_parallized(1) <= V2_parallized(0); end if; end process; -- V3 process(V3_sync_signal,clk160, reset) begin if reset = '1' then V3_parallized(0) <= '0'; elsif clk160'event and clk160 = '1' then V3_parallized(0) <= V3_sync_signal; end if; end process; process(V3_parallized(0),clk160, reset) begin if reset = '1' then V3_parallized(1) <= V3_parallized(0); elsif clk160'event and clk160 = '1' then V3_parallized(1) <= V3_parallized(0); end if; end process; counter_logic: for ii in 1 to 24 generate begin -- input selector process(clk160, clk_en0deg, analyzer_pattern_sel_input_reg_signal(ii), T0_parallized, V0_parallized, V1_parallized, V2_parallized, V3_parallized) begin if clk160'event and clk160 = '1' and clk_en0deg = '1' then case analyzer_pattern_sel_input_reg_signal(ii) is when "000" => analyzer_sig0(ii) <= T0_parallized(1 downto 0); when "001" => analyzer_sig0(ii) <= V0_parallized(1 downto 0); when "010" => analyzer_sig0(ii) <= V1_parallized(1 downto 0); when "011" => analyzer_sig0(ii) <= V2_parallized(1 downto 0); when "100" => analyzer_sig0(ii) <= V3_parallized(1 downto 0); when others => analyzer_sig0(ii) <= "00"; end case; end if; end process; analyzer_sig1(ii) <= '1' when ((analyzer_sig0(ii)(1 downto 0) = analyzer_pattern_in_reg_signal(ii)(1 downto 0)) and (selected_trigger_signal(3 downto 0) = analyzer_pattern_out_reg_signal(ii)(3 downto 0) or analyzer_pattern_coinz_en_reg_signal(ii) = '0' )) else '0'; process(clk160, clk_en0deg, reset, analyzer_sig1(ii)) begin if reset = '1' then analyzer_counter_en(ii) <= '0'; elsif clk160'event and clk160 = '1' and clk_en0deg = '1' then analyzer_counter_en(ii) <= analyzer_sig1(ii); end if; end process; end generate; -- ######################################################## -- ############# outputs ################################## -- ######################################################## selected_trigger_signal <= fiber_output_pattern_reg_signal when fiber_output_pattern_en_reg_signal = '1' else LUT_trigger_signal; process(clk160, reset, clk_en90deg, selected_trigger_signal) begin if reset = '1' then selected_trigger_signal_reg <= "0000"; elsif clk160'event and clk160='1' and clk_en90deg = '1' then selected_trigger_signal_reg <= selected_trigger_signal; end if; end process; Inst_fiber_encode: fiber_encode PORT MAP( clk40 => clk40, clk160 => clk160, LUT_data(3 downto 0) => selected_trigger_signal_reg, encoded_signal => encoded_signal, clk_en_first_bit_marker => clk_en0deg, reset => reset ); -- address for timing analyze readout readout_address_data_analyze_signal <= scsn_addr_signal(8 downto 0); Inst_timing_analyze_module: timing_analyze_module PORT MAP( activate => activate_timing_analyze_reg_signal, reset => reset, clear => clear_timing_analyze_reg_signal, done => done_timing_analyze_signal, signals(0) => q(2), -- for automatic triggering signals(1) => '0', -- T0_sync_signal, signals(2) => '0', -- V0_sync_signal, signals(3) => encoded_signal, --q(5),---V1_sync_signal, signals(4) => CB_TOF_sig, signals(8 downto 5) => selected_trigger_signal_reg, --q(6),--V2_sync_signal, signals(10 downto 9) => "00", signals(11) => T0_sync_signal, signals(12) => V0_sync_signal, signals(13) => V1_sync_signal, signals(14) => V2_sync_signal, signals(15) => V3_sync_signal, signals(16) => '0', signals(17) => '0', signals(19 downto 18) => T0_parallized_signal, signals(21 downto 20) => V0_parallized_signal, signals(23 downto 22) => V1_parallized_signal, signals(25 downto 24) => V2_parallized_signal, signals(27 downto 26) => V3_parallized_signal, signals(31 downto 28) => zero_signal(31 downto 28), clk => clk160, clk_scsn => clk_scsn, readout_value => readout_value_data_analyze_signal, readout_address => readout_address_data_analyze_signal, trigger_mask => timing_analyze_trigger_pattern_reg_signal ); -- register scsn data from timing analyze module to do proper timing process(clk_scsn, reset, readout_value_data_analyze_signal) begin if reset = '1' then readout_value_data_analyze_signal_reg <= X"00000000"; elsif clk_scsn'event and clk_scsn='1' then readout_value_data_analyze_signal_reg <= readout_value_data_analyze_signal; end if; end process; LED2 <= '0'; --CB_TOF <= encoded_signal;--LUT_data_out_signal(0); process(clk40, reset) begin if reset = '1' then ds_count <= ( others => '0'); elsif clk40'event and clk40='1' then ds_count <= ds_count + 1; end if; end process; process(cbtof_src, encoded_signal, ds_count) begin case cbtof_src is when "001" => CB_TOF_sig <= encoded_signal; when "010" => CB_TOF_sig <= ds_count(15); when "100" => CB_TOF_sig <= '0'; when "110" => CB_TOF_sig <= '1'; when others => CB_TOF_sig <= encoded_signal; end case; end process; process(spare_src, encoded_signal, ds_count) begin case spare_src is when "001" => spare <= encoded_signal; when "010" => spare <= ds_count(15); when "100" => spare <= '0'; when "110" => spare <= '1'; when others => spare <= '0'; end case; end process; CB_TOF <= CB_TOF_sig; L_OUTS <= spare; T7 <= FEB_KOINZ_signal(1);--clk40;--L1ACCEPT; -- so this DCS-Board can be used as Trigger receiver T2 <= encoded_signal; --SCSNFEBIN; end BEHAVIORAL;