Commisioning guide for the pretrigger
=====================================

load the fpga design
====================
-1) cd /dcsnfs/pretrigger
0) change to the right jtag driver @ cbx and @ cbtof
             rmmod jtag
             insmod jtagfeb.o
1) load CBTOF: @CBTOF ./playxsvf -t /dev/jtagfeb cbtofhans.xsvf
2) load CBC: @CBC echo "2" > /dev/jtagsel
             @CBC ./playxsvf -t /dev/jtagfeb cbcfpga.xsvf
3) load FEB: @CBC echo "3" > /dev/jtagsel
             @CBC ./playxsvf -t /dev/jtagfeb febfpga_chain.xsvf

calibrate FEB to CBC connection
===============================
# 0) @CBC set FEB to configuration mode ./CheshireCat CB_write 999 {1..5} 
1) @FEB all inputs to pulser (done by ./FEB_sync.sh)
2) @FEB all pulser disable exept for no 0 (done by ./FEB_sync.sh)
3) @FEB set pulser_period no 0 to 15 (done by ./FEB_sync.sh)
4) @FEB config LUT all 0 exept for 32769 set this 1 (done by ./FEB_sync.sh)
5) @CB select FEB to watch ./CheshireCat CB_write 999 {1..5}
   check @ FEB (./FEB_counter_readout_CheshireCat.sh)
   trigger paralell(0) increases (counter no 13)
   trigger paralell(1) stays equal (counter no 14)
6) @ CBX set FEB to trigger sending 
   ./CheshireCat CB_write 999 0
7) check @ CBX that pattern_sync_edge_rate is constant 
   (./CheshireCat CB_read 3{1..5}2),
   if not change pattern_sync_edge_sel
   (./CheshireCat CB_write 3{1..5}0 0/1),
8) check @ CBX that only xx_pattern_paralized_signal(0) (for T0 counter 27)
   increases and xx_paralized_signal(1) (for T0 counter 28) stays equal,
   if not add pattern_sync_delay
9) Check @ CBX analyzer that all FEB inputs fire at the same time
   use a low luminosity Run and the timing analyzer
   only delay in steps of 4

calibrate CBC to CBTOF connection
=================================
1) @CBC
   fiber_output_pattern_mode = 1 (./CheshireCat CB_write 360 1)
   fiber_output_pattern = 3 (./CheshireCat CB_write 361 3)
2) check @CBTOF rate_measurement that it is constant 
   (./CheshireCat CB_read 2{1..0}2 )
   if not change latching edge (./CheshireCat CB_write 2{1..0}0 1/0
3) @CBC
   fiber_output_pattern_en = 1 (./CheshireCat CB_write 360 1)
   fiber_output_pattern = 4 (./CheshireCat CB_write 361 4)
4) @CBTOF set match_pattern 4 (./CheshireCat CB_write 800 4 (cb_a)(or 810 for cb_c)
5) @CBTOF check LUT_pattern_match signal increasing like clk_counter (counter 8..9)
   if not add delay ./CheshireCat CB_write 201 0..31 (CB_A) or 
   ./CheshireCat CB_write 211 0..31 (CB_C)
   or shift the clock ./CheshireCat CB_write 99 0..3


Make the system ready for pretrigger; one PMT from T0 should fire
==========================================================================
0) @CBC switch to FEB config mode ./CheshireCat CB_write 999 {1..5} (done by FEB_trigger.sh)
1) @CBC switch all FEB inputs to normal mode (done by FEB_trigger.sh)
2) @CBC set thresholds for FEB inputs (done by FEB_trigger.sh)
2) @CBC load FEB LUT config ./CheshireCat FEB_LUT_config (done by FEB_trigger.sh)
3) @CBC switch FEB back to trigger mode (done by FEB_trigger.sh)
4) @CBC disable all inputs exept for T0 by setting to patterngen with 0 pattern(done by CBC_disable_V0)
3) @CBC load CBC LUT config ./CheshireCat CBC_LUT_config
4) @CBC switch to trigger mode instead of pattern mode ./CheshireCat CB_write 360 0
4) @CBTOF load CBTOF LUT config ./CheshireCat CBTOF_LUT_config
5) 

Make a internal puls at FEB T0 input 0 be send to the whole trigger
===================================================================
0) @CBC go to FEB configuration mode ./CheshireCat CB_write 999 5
0) @CBC set FEB to sync mode (send a 1 every 5 cycles) ./FEB_sync.sh
1) @CBC go to FEB trigger mode ./CheshireCat CB_write 999 0
2) @CBC got to CBC trigger mode instead of pattern sending 
   ./CheshireCat CB_write 360 0
1) @CBC disable all FEB inputs exept for T0 ./CBC_disable_V0.sh
2) @CBC config cbc_lut to make a 1 from T0 to a 10 to CB_TOF ./CheshireCat CBC_LUT_config
3) @CBC check only counter 27 (FEB bit 0), 42, 43, 45 (output to CBTOF), 
   but not counter 44 (output to CBTOF) should increase.
   42 should 5 times be lager than 43 and 45. (send a 10 for every trigger else a 1)
4) @CBTOF check that the bitpattern arrives for CB_A see counters 16 to 19
   look for the distribution on the bits 
   counter_16 = 5*counter_17 = 5*counter_19
   either adjust the delay of cb_a or shift clk_pase ./CheshireCat CB_write 99 0..3
3) @CBTOF config cbtof_lut to fire a trigger if a 10 arrives from CBC
          ./CheshireCat CBTOF_LUT_config