===================================== Pretrigger CheshireCat Manual for FEB ===================================== IMPORTANT: execute all commands at the CBC / CBA DCS board select_feb_to_configure ./CheshireCat CB_write 999 0..5 -- 5 for T0 FEB -- 1 for V0 FEB -- 2 for V1 FEB -- 3 for V2 FEB -- 4 for V3 FEB -- 0 to switch to normal trigger operation configure FPGA ============== mount dcsnfs nfsmount zimmer://home/stefan/CheshireCat/dcsnfs remove std. driver rmmod jtag load jtag driver insmod jtagfeb.o select jtag line echo '3' > /dev/jtagsel load design ./playxsvf -t /dev/jtagfeb febfpga.xsvf LUT configuration ================== LUT_data_in_signal ./CheshireCat FEB_write 32768..36863 0..3 LUT_data_out_signal ./CheshireCat FEB_read 32768..36863 select outphase ./CheshireCat FEB_write 99 0..3 trigger output to CBC/A configuration ===================================== fiber_output_pattern_en ./CheshireCat CB_write 360 0/1 fiber_output_pattern ./CheshireCat CB_write 361 0..15 timing analyzer =============== clear timing analyzer ./CheshireCat FEB_write 600 1..0 set trigger pattern ./CheshireCat FEB_write 601 0..65535 active timing analyze ./CheshireCat FEB_write 602 1..0 read timing analyze ./CheshireCat FEB_read 16384 ... 16895 ./CheshireCat FEB_analyzer_read done timing analyze ./CheshireCat FEB_read 603 counter readout =============== counter_reset ./CheshireCat FEB_write 50 0/1 counter_readout_req ./CheshireCat FEB_write 51 0/1 counter_readout_done ./CheshireCat FEB_read 52 counter_value(31 downto 0) ./CheshireCat FEB_read 6400 + CounterNo counter_value(48 downto 32) ./CheshireCat FEB_read 12800 + CounterNo counter Channels counter_en(0) => '1', counter_en(12 downto 1) => DET_sync_signal(11 downto 0), counter_en(13) => trigger_paralell(0), counter_en(14) => trigger_paralell(1), counter_en(62 downto 15) => zero_signal(62 downto 15), set trigger thresholds ====================== DET_update ./CheshireCat FEB_write 799 0..1 DET_threshold(0) ./CheshireCat FEB_write 700 0..255 DET_threshold(1) ./CheshireCat FEB_write 701 0..255 DET_threshold(2) ./CheshireCat FEB_write 702 0..255 DET_threshold(3) ./CheshireCat FEB_write 703 0..255 DET_threshold(4) ./CheshireCat FEB_write 704 0..255 DET_threshold(5) ./CheshireCat FEB_write 705 0..255 DET_threshold(6) ./CheshireCat FEB_write 706 0..255 DET_threshold(7) ./CheshireCat FEB_write 707 0..255 DET_threshold(8) ./CheshireCat FEB_write 708 0..255 DET_threshold(9) ./CheshireCat FEB_write 709 0..255 DET_threshold(10) ./CheshireCat FEB_write 710 0..255 DET_threshold(11) ./CheshireCat FEB_write 711 0..255 set input delays ================ DET_delay(0) ./CheshireCat FEB_write 2200 0..255 DET_delay(1) ./CheshireCat FEB_write 2201 0..255 DET_delay(2) ./CheshireCat FEB_write 2202 0..255 DET_delay(3) ./CheshireCat FEB_write 2203 0..255 DET_delay(4) ./CheshireCat FEB_write 2204 0..255 DET_delay(5) ./CheshireCat FEB_write 2205 0..255 DET_delay(6) ./CheshireCat FEB_write 2206 0..255 DET_delay(7) ./CheshireCat FEB_write 2207 0..255 DET_delay(8) ./CheshireCat FEB_write 2208 0..255 DET_delay(9) ./CheshireCat FEB_write 2209 0..255 DET_delay(10) ./CheshireCat FEB_write 2210 0..255 DET_delay(11) ./CheshireCat FEB_write 2211 0..255 set input sampling phase ======================== DET_phase_reg_signal(0) ./CheshireCat FEB_write 2100 0..3 DET_phase_reg_signal(1) ./CheshireCat FEB_write 2101 0..3 DET_phase_reg_signal(2) ./CheshireCat FEB_write 2102 0..3 DET_phase_reg_signal(3) ./CheshireCat FEB_write 2103 0..3 DET_phase_reg_signal(4) ./CheshireCat FEB_write 2104 0..3 DET_phase_reg_signal(5) ./CheshireCat FEB_write 2105 0..3 DET_phase_reg_signal(6) ./CheshireCat FEB_write 2106 0..3 DET_phase_reg_signal(7) ./CheshireCat FEB_write 2107 0..3 DET_phase_reg_signal(8) ./CheshireCat FEB_write 2108 0..3 DET_phase_reg_signal(9) ./CheshireCat FEB_write 2109 0..3 DET_phase_reg_signal(10) ./CheshireCat FEB_write 2110 0..3 DET_phase_reg_signal(11) ./CheshireCat FEB_write 2111 0..3 input pulser ============ pulser_mode(0) ./CheshireCat FEB_write 2300 0..1 pulser_en ./CheshireCat FEB_write 2500 0..1 pulser_pause_after_puls(0) ./CheshireCat FEB_write 2400 0..255 pulser_mode(1) ./CheshireCat FEB_write 2301 0..1 pulser_en(1) ./CheshireCat FEB_write 2501 0..1 pulser_pause_after_puls(1) ./CheshireCat FEB_write 2401 0..255 pulser_mode(2) ./CheshireCat FEB_write 2302 0..1 pulser_en(2) ./CheshireCat FEB_write 2502 0..1 pulser_pause_after_puls(2) ./CheshireCat FEB_write 2402 0..255 pulser_mode(3) ./CheshireCat FEB_write 2303 0..1 pulser_en(3) ./CheshireCat FEB_write 2503 0..1 pulser_pause_after_puls(3) ./CheshireCat FEB_write 2403 0..255 pulser_mode(4) ./CheshireCat FEB_write 2304 0..1 pulser_en(4) ./CheshireCat FEB_write 2504 0..1 pulser_pause_after_puls(4) ./CheshireCat FEB_write 2404 0..255 pulser_mode(5) ./CheshireCat FEB_write 2305 0..1 pulser_en(5) ./CheshireCat FEB_write 2505 0..1 pulser_pause_after_puls(5) ./CheshireCat FEB_write 2405 0..255 pulser_mode(6) ./CheshireCat FEB_write 2306 0..1 pulser_en(6) ./CheshireCat FEB_write 2506 0..1 pulser_pause_after_puls(6) ./CheshireCat FEB_write 2406 0..255 pulser_mode(7) ./CheshireCat FEB_write 2307 0..1 pulser_en(7) ./CheshireCat FEB_write 2507 0..1 pulser_pause_after_puls(7) ./CheshireCat FEB_write 2407 0..255 pulser_mode(8) ./CheshireCat FEB_write 2308 0..1 pulser_en(8) ./CheshireCat FEB_write 2508 0..1 pulser_pause_after_puls(8) ./CheshireCat FEB_write 2408 0..255 pulser_mode(9) ./CheshireCat FEB_write 2309 0..1 pulser_en(9) ./CheshireCat FEB_write 2509 0..1 pulser_pause_after_puls(9) ./CheshireCat FEB_write 2409 0..255 pulser_mode(10) ./CheshireCat FEB_write 2310 0..1 pulser_en(10) ./CheshireCat FEB_write 2510 0..1 pulser_pause_after_puls(10) ./CheshireCat FEB_write 2410 0..255 pulser_mode(11) ./CheshireCat FEB_write 2311 0..1 pulser_en(11) ./CheshireCat FEB_write 2511 0..1 pulser_pause_after_puls(11) ./CheshireCat FEB_write 2411 0..255