====================================== Pretrigger CheshireCat Manual for CBTOF ====================================== reset module ./CheshireCat CB_reset controlling TIN proxy no xxx (signature 83+xxx) =============================================== xxx = 0 .. 5 ctp mode ./CheshireCat CB_write 20+xxx 0..3 0 normal mode 1 toggling mode 2 send signature (83+xxx) 3 send random trigger ctp mode readback ./CheshireCat CB_read 20+xxx rand. trigger threshold ./CheshireCat CB_write 30+xxx 0..2147483648 Syncronizing the inputs ========================= CB_A set latching edge: ./CheshireCat CB_write 200 0/1 set delay ./CheshireCat CB_write 201 0..31 rate measurement: ./CheshireCat CB_read 202 CB_C set latching_edge: ./CheshireCat CB_write 210 0/1 set delay ./CheshireCat CB_write 211 0..31 rate measurement: ./CheshireCat CB_read 212 T0 set latching_edge: ./CheshireCat CB_write 220 0/1 set delay ./CheshireCat CB_write 221 0..31 rate measurement: ./CheshireCat CB_read 222 T1 set latching_edge: ./CheshireCat CB_write 230 0/1 set delay ./CheshireCat CB_write 231 0..31 rate measurement: ./CheshireCat CB_read 232 T2 set latching_edge: ./CheshireCat CB_write 240 0/1 set delay ./CheshireCat CB_write 241 0..31 rate measurement: ./CheshireCat CB_read 242 T3 set latching_edge: ./CheshireCat CB_write 250 0/1 set delay ./CheshireCat CB_write 251 0..31 rate measurement: ./CheshireCat CB_read 252 T4 set latching_edge: ./CheshireCat CB_write 260 0/1 set delay ./CheshireCat CB_write 261 0..31 rate measurement: ./CheshireCat CB_read 262 T5 set latching_edge: ./CheshireCat CB_write 270 0/1 set delay ./CheshireCat CB_write 271 0..31 rate measurement: ./CheshireCat CB_read 272 T6 set latching_edge: ./CheshireCat CB_write 280 0/1 set delay ./CheshireCat CB_write 281 0..31 rate measurement: ./CheshireCat CB_read 282 T7 set latching_edge: ./CheshireCat CB_write 290 0/1 set delay ./CheshireCat CB_write 291 0..31 rate measurement: ./CheshireCat CB_read 292 GTU_Busy first edge sel: ./CheshireCat CB_write 303 0..1 xor clk phase: ./CheshireCat CB_write 304 0.. set latching edge: ./CheshireCat CB_write 300 0..1 set delay: ./CheshireCat CB_write 301 0..31 rate measurement: ./CheshireCat CB_read 302 timing analyzer =============== clear timing analyzer ./CheshireCat CB_write 600 1..0 set trigger pattern ./CheshireCat CB_write 602 0..65535 active timing analyze ./CheshireCat CB_write 601 1..0 read timing analyze ./CheshireCat CB_read 16384 ... 16895 ./CheshireCat CB_analyzer_read done timing analyze ./CheshireCat CB_read 603 Controll the trigger processing ================================ TOF_signal_to_scintil ./CheshireCat CB_write 130 0..7 clk_TTCex_shifts ./CheshireCat CB_write 99 0..3 disable_GTU_BUSY ./CheshireCat CB_write 399 0..1 disable_SOR_EOR_busy ./CheshireCat CB_write 499 0..1 tp_scintillator_en ./CheshireCat CB_write 100 0/1 tp_LUT_as_pre_en ./CheshireCat CB_write 101 0/1 tp_CTP_as_pretrig_en ./CheshireCat CB_write 102 0/1 tp_L0_en ./CheshireCat CB_write 103 0/1 tp_L1_en ./CheshireCat CB_write 104 0/1 tof_signal_to_scintil ./CheshireCat CB_write 130 0..7 LUT_L0_to_CTP_en ./CheshireCat CB_write 120 0/1 scintillator_to_CTP_en ./CheshireCat CB_write 121 0/1 Pre_from_LUT_to_CTP_en ./CheshireCat CB_write 122 0/1 Software_trig_to_CTP_en ./CheshireCat CB_write 123 0/1 tp_pre_to_next_cycles ./CheshireCat CB_write 106 1..65536 tp_L0_to_next_cycles ./CheshireCat CB_write 107 (ctp_L0-L1)..65536 set to (desired rising'edge to rising'edge time) minus 3 for L1 output at least ctp L0-L1 time tp_L1_to_next_cyles ./CheshireCat CB_write 108 0..65536 set to 0 (minimal L1-rising'edge to next pre-rising'edge = 2) set to (minimal L1_resing'edge to next pre-rising'edge) minus 4 tp_L0_autogen ./CheshireCat CB_write 109 0/1 tp_L1_autogen ./CheshireCat CB_write 110 0/1 B_channel_disable ./CheshireCat CB_write 48 0/1 TTCex_clk_disable ./CheshireCat CB_write 49 0/1 LUT_L0_en ./CheshireCat CB_write 120 0/1 pre_as_L0_en ./CheshireCat CB_write 121 0/1 dissable_trigger_to_SM ./CheshireCat CB_write 199 0/1 tp_software_trigger_en ./CheshireCat CB_write 105 0/1 software_trigger_start ./CheshireCat CB_write 350 0/1 software trigger patte ./CheshireCat CB_write 351 0..255 Configure the trigger Logic ========================== write data to LUT ./CheshireCat CB_write 32768..40959 0..3 read data from LUT ./CheshireCat CB_read 32768..40959 counter module ============== reset_counters ./CheshireCat CB_write 50 0/1 start readout ./CheshireCat CB_write 51 0/1 readout done ./CheshireCat CB_read 52 get low bits ./CheshireCat CB_read 6400 + counter no get high bits ./CheshireCat CB_read 12800 + counter no set matching pattern for pattern match counter match_pattern_cb_a ./CheshireCat CB_write 800 0..15 match_pattern_cb_c ./CheshireCat CB_write 810 0..15 match_pattern_tof ./CheshireCat CB_write 820 0..31 meaning of the different counters counter_en(0) => '1', counter_en(1) => trigger_to_SM_reg, counter_en(2) => pretrigger_bussy, counter_en(3) => pre_signal, -- produced from CTP and/or LUT and/or L1 counter_en(4) => L0_signal, -- from CTP counter_en(5) => L1_signal, -- from CTP counter_en(6) => LUT_L0_signal_TTC_reg,-- L0 produced by the LUT counter_en(7) => not TIN_to_CTP_Pre_signal, -- sent to CTP counter_en(8) => LUT_pattern_match_cb_a_signal, counter_en(9) => LUT_pattern_match_cb_c_signal, counter_en(10) => LUT_pattern_match_tof_signal, counter_en(11) => trigger_scintillator_signal, counter_en(12) => trigger_to_SM_reg, counter_en(13) => LUT_pre_signal, -- compare LUT_pre_signal counter to -- scintillator_pretirg_signal counter -- and you know about the quality of the pretrigger -- configuration counter_en(14) => missing_pre_signal, counter_en(15) => unneccessary_pre_signal, counter_en(28 downto 16) => LUT_monitoring_signal(12 downto 0), counter_en(62 downto 29) => zero_signal(62 downto 29) configuring the coinz modules for the counter ============================================= coinz1_delay ./CheshireCat CB_write 980 0..511 coinz2_delay ./CheshireCat CB_write 981 0..511 coinz3_delay ./CheshireCat CB_write 982 0..511 coinz_mode(counter x) ./CheshireCat CB_write 900..962 0..3 (0 raw, 1 to Pre, 2 to L0, 3 to L1) copy files into the nfs ======================= cd /home/stefan/CheshireCat/dcsnfs tar -cf ../dcsnfs.tar * scp /home/stefan/CheshireCat/dcsnfs.tar trd@pcalitrd00.cern.ch://home/trd/users/szimmer/dcsnfs.tar ssh trd@pcalitrd00.cern.ch scp /home/trd/users/szimmer/dcsnfs.tar trd@wn5:/home/trd/dcsnfs/pretrigger/dcsnfs.tar ssh wn5 cd /home/trd/dcsnfs/pretrigger/ tar -xf dcsnfs.tar configure FPGA ============== mount dcsnfs nfsmount zimmer://home/stefan/CheshireCat/dcsnfs remove std. driver rmmod jtag load jtag driver insmod jtagfeb.o select jtag echo '2' > /dev/jtagsel load design ./playxsvf -t /dev/jtagfeb cbtofhans.xsvf