\chapter{CPLD design and J2C interface}
\label{j2c}
%  svn Id  : $Id$


%-----------------------------------------------------------------------------
\section{CPLD resynchronization design}
\label{j2c:cpld_res}

A circuit similar to that in the TRAP chip implements the DDR to SDR
conversion and the resynchronization (see Fig. \ref{fig:cpld_res}) in the CPLD.

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_j2c/cpld_res.eps}
 \caption[Block diagram of the CPLD resynchronization]{Block diagram of the CPLD resynchronization}
 \label{fig:cpld_res}
\end{figure}

There are four input registers for each edge (pos/neg) of the strobe signal. A Grey
counter GCNTp, triggered by the corresponding strobe edge, controls the
write enables to the data registers. GCNTp is copied to a register GREG
in the output clock domain. If any difference is detected between the
GREG and GCNTc, the data valid is set and the gray counter GCNTc is
enabled for one clock. The output data and the valid flag are synchronized
again with the output clock and are fed to the serializer inputs.
The clock resynchronization is necessary, because the serializers normally
require a very high clock quality, which is hardly to achieve with the
clock distribution on the readout board.

The proposed resynchronization technique has the lowest possible
latency and size.

\begin{figure}[htb]
 \centering
 \includegraphics*[width=12cm]{chap_j2c/latency.eps}
 \caption[The latency of the CPLD resynchronization]{The latency of the CPLD resynchronization}
 \label{fig:cpld_latency}
\end{figure}



\section{J2C interface}
\label{j2c:j2c_int}


The J2C interface is similar to I2C, but requires much less resources in the CPLD and uses only the
JTAG signals (see fig.\ref{fig:block_jt_j2c}). The idea is to have TMS=1 always when TCK has a rising
edge. This ensures, that the JTAG state machine in the CPLD remains undisturbed. The data are shifted
LSB first with the rising edge of the TCK. Each J2C transaction consists of two phases: command and
data. The command is 4 bit, the MSB is 1 for writing and 0 for reading, the remaining 3 bits are used
as address. Note that the address bits can be extended, but for the ORI design 8 internal registers are
enough. The data are transfered from the master to the slave with the rising TCK edge and from the slave to
the master with the falling edge of TCK. Thus the master drives TDI before and shortly after the TCK rising
edge, then the slave drives the TDO and the master samples (only when reading) the data while the TCK is
high. After the command phase, the TCK and TDI remain 0/1, TMS makes a negative pulse (to low and back to
high). This latches the command and the address in the slave. Now comes the data phase. After all 8 bits are
shifted, the TCK and TDI remain 0, TMS makes a negative pulse and this latches the data in the slave (when
writing) or just marks the end of the transaction.

A example of a J2C write transaction is shown on the next fig.\ref{fig:j2c_wr}. The names
of the signals correspond to the signal names on the right (ROB and TRAP) side in fig.\ref{fig:block_jt_j2c}.

For using J2C the signal DIS\_JTG must be 0.

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_j2c/j2c_write.eps}
 \caption[Example of J2C write transaction]{Example of J2C write transaction}
 \label{fig:j2c_wr}
\end{figure}

The next example is reading fig.\ref{fig:j2c_rd}.

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_j2c/j2c_read.eps}
 \caption[Example of J2C read transaction]{Example of J2C read transaction}
 \label{fig:j2c_rd}
\end{figure}


\section{CPLD configuration}
\label{j2c:cpld}

The position of the parity and spare bits can be set similar to the TRAP NPx registers. The reset values are
the same. The address for reading is 4 or 5, for writing can be any even address (0, 2, 4, 6).

\register{SPAPAR}{4}{TRAP NI input port spare and parity bits}
{Bit positions and control signal for the input ports}
{ffff pppp}
{1001 1000}
{p & position of parity bit (after spare)\\
 f & position of spare bit (extracted first), only these 4 bits are with hamming protection\\
}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=10cm]{chap_j2c/excl.eps}
 \caption[Functionality of bit excluding]{The parity and a spare bit are added to the 10~Bit
 output whereby the position can be freely chosen via the \reg{NED.p} and \reg{NED.f} registers in the
 TRAP and \reg{SPAPAR.p} and \reg{SPAPAR.f} register in the ORI.
 The input port in ORI extracts the two bits. This allows a fault tolerance in case of static bit errors.}
 \label{fig:excl}
\end{figure}

Values of the spare position above 9 have no sense, but in the current design are used to enter some special
operating modes, where the input data are irrelevant.

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|c|l|}\hline
spare bit position & Description\\\hline\hline
0..8 & normal operation, position of the spare bit 0..8\\\hline
9, 13, 15 & normal operation, position of the spare bit 9\\\hline
10 & activate the PRBSEN pin of the TLK2501 chip (send test-pattern)\\\hline
11 & enable writing to the serial EEPROM (otherwise disabled)\\\hline
12 & send test-pattern from the CPLD\\\hline
14 & shutdown only the analog part of the ORI, useful to reset the laser driver chip\\\hline
\end{tabular}
\caption[Special modes of operation]{Special modes of operation chosen via the SPAPAR register}
 \label{tab:ori_mode}
\end{table}

The test-pattern send by the CPLD is very simple. The 16-bit data consists of 4 nibble (4-bit) counters, the
outer counting up, the inner counting down. The initial value can be different. If the ORI was reseted and then
without sending any data programmed into test-pattern mode, the pattern will be:

\verb+0x0000, 0x1ff1, 0x2ee2, 0x3dd3, 0x4cc4, 0x5bb5, 0x6aa6, 0x7997,+

\verb+0x8888, 0x9779, 0xa66a, 0xb55b, 0xc44c, 0xd33d, 0xe22e, 0xf11f, 0x0000...+

Otherwise the test-pattern counters will just start from the last data sent.


Note: Writing to any address resets the resynchronization unit and the counters N16W, NBWPF, NBWPL!

The rest of the registers are status (read only).

\register{N16W.L}{0}{Word counter (L)}
{Lower 8 bits of the number of transmitted 16 bit words}
{LLLL LLLL}
{0000 0000}
{L & number of 16-bit words transmitted (lower 8 bits)\\
}

\register{N16W.H}{1}{Word Counter (H) and FAULT}
{Upper 8 bits of the number of transmitted 16 bit words and FAULT pin of the LTC chip}
{FHHH HHHH}
{1000 0000}
{F & FAULT pin of the LTC chip, programmed there as active low, so FAULT=1 is good!\\
 H & number of 16-bit words transmitted (upper 7 bits)\\
}

The counter \reg{N16W} wraps after 0x7FFF to 0x000.

\register{NBWPF}{2}{Parity counter (falling)}
{FAULT of the LTC and a 7 bit counter for the number of bytes with wrong parity at the falling edge of the strobe}
{FNNN NNNN}
{1000 0000}
{F & FAULT pin of the LTC chip, programmed there as active low, so FAULT=1 is good!\\
 N & number of bytes with wrong parity, transmitted at the falling edge of the strobe\\
}

\register{NBWPR}{3}{Parity counter (rising)}
{FAULT of the LTC and a 7 bit counter for the number of bytes with wrong parity at the rising edge of the strobe}
{FRRR RRRR}
{1000 0000}
{F & FAULT pin of the LTC chip, programmed there as active low, so FAULT=1 is good!\\
 R & number of bytes with wrong parity, transmitted at the rising edge of the strobe\\
}

Note: Both \reg{NBWPF} and \reg{NBWPR} clip at 0x7F. All three counters are reseted when writing to any
address through the J2C interface.

The last read only register at addresses 6 or 7 contains the status of the hamming decoder of the
upper 4 bits of the \reg{SPAPAR} register and the firmware version.

\register{HSVER}{6}{Hamming status and Version}
{Hamming status of the SPAPAR.f register and version of the CPLD design}
{S-VV VVVV}
{0000 1000}
{S & hamming status of the upper part of SPAPAR register (only the upper 4 bits are hamming protected),
should be 0 for no errors\\
 V & version of the CPLD design, one-hot coded. The current is 8.\\
}
