\chapter{Introduction}
\label{intro}
%  svn Id  : $Id$


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\section{Overview}
\label{intro:ov}

The ALICE TRD Detector employs 1080 optical links for the data readout.
The FEE chips (TRAP) form a readout tree running at 8 bit 120 MHz
double data rate. The Optical Readout Interface (ORI) performs LVDS to
LVCMOS level translation, double to single data rate (DDR to SDR)
conversion, data resynchronization, serialization and optical transmission
at 2.5 Gbit/s.

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_intro/ori.eps}
 \caption[Block diagram of the ORI board]{Block diagram of the ORI board}
 \label{fig:block_ori}
\end{figure}

The module is built using commercially available components. Texas
Instruments TLK2501 is used as serializer, Linear Technology LTC5100 as
optical driver for a VCSEL diode at 850nm from ULM. The interface between
TRAP output and TLK input is implemented using a Lattice CPLD ispMACH 4k.
A CPLD is sufficient for the interface logic and is favoured over a FPGA
because of its better radiation tolerance and as no configuration memory is needed.
The application of a freely configurable CPLD makes this low-cost device
adoptable to a large range of driving signal standards.
The TRAP chip drives 10 data lines - 8 data bits, a parity and a spare
bit - along with a strobe signal. The positions of the parity/spare bits
within the 10 data lines are freely programmable. This feature is implemented
in the CPLD design as well. The TRAP provides the data with each edge of
the strobe signal. When no data are sent, the strobe remains high.

