\chapter{I2C interface and I2C devices}
\label{i2c}
%  svn Id  : $Id$


%-----------------------------------------------------------------------------
\section{Architecture}
\label{i2c:arch}

The block diagram \ref{fig:block_i2c} shows the interconnection between the readout board and the I2C
devices through the CPLD in case of I2C communication.

\begin{figure}[htb]
 \centering
 \includegraphics*[width=13cm]{chap_i2c/blockd.eps}
 \caption[Block diagram of the ORI in I2C mode]{Block diagram of the ORI in I2C mode}
 \label{fig:block_i2c}
\end{figure}

The DIS\_JTG signal must be 1. In this case SCL=1 in
the TRAP puts the SCL on the ORI board in tri-state mode, SCL=0 in the TRAP pulls down the SCL on the ORI
board. Similarly, SDA\_OUT=1 in the TRAP puts the SDA on the ORI board in tri-state mode, SDA\_OUT=0 in the
TRAP pulls down the SDA on the ORI board. The SDA on the ORI board can be read back in the TRAP chip as
SDA\_IN.

If DIS\_JTG=0 the interface is in JTAG/J2C mode, both SDA and SCL lines on the ORI board are tri-stated.

Locally on the ORI board there are two I2C devices, the laser driver chip (LTC5100) and its serial
configuration EEPROM (24LC01).

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|c|c|l|l|l|}\hline
Chip & 8 bit I2C device Id (as for writing) & Description & Dataword size & Internal addresses\\\hline\hline
24LC01 & 0xAE & serial EEPROM 256 x 8 & 8 bit (byte) & 0..255\\\hline
LTC5100 & 0x14 & laser driver & 16 bit & 0..31 (not all)\\\hline
\end{tabular}
\caption[I2C devices in ORI]{I2C devices in ORI}
 \label{tab:i2c_dev}
\end{table}


\section{Configuration EEPROM memory}
\label{i2c:eep}

\subsection{Serial number field in the EEPROM}
\label{i2c:eep-sernr}

The configuration EEPROM memory chip has 256 bytes. The LTC chip expects its configuration at addresses 0x60 to 0x6F. The
rest of the address space is free for user data. All ORI boards have the serial number stored in the unused space, see
\ref{tab:sernr}. The serial Nr. is in BCD (binary coded decimal) representation. For example serial Nr. 1023 (decimal) will
be stored as 0x10 (upper byte) and 0x23 (lower byte).

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|c|l|}\hline
Address & Value\\\hline\hline
0x00 & Serial Nr. MSC, lower Byte = Serial Nr. ALICE lower Byte\\\hline
0x01 & Serial Nr. MSC, upper Byte = Serial Nr. ALICE upper byte only for ORIs produced after 05.2007.\\\hline
0x02 & 0x62 (05.2006), 0x23 (09.2006), 0x24 (10.2006), 0x00 (05.2007)\\\hline
0x03 & 0x06 (05.2006), 0x11 (09.2006), 0x11 (10.2006), 0x00 (05.2007)\\\hline
0x04 & 0x06 (2006), 0x00 (2007)\\\hline
0x05 & 0x02 (2006), 0x00 (2007)\\\hline
0x10 & Serial Nr. ALICE lower Byte\\\hline
0x11 & Serial Nr. ALICE upper Byte\\\hline
0x12 & Contains 0x99 if the write protection test of the EEPROM was successful\\\hline
\end{tabular}
\caption[Serial Nr. stored in the EEPROM]{Serial Nr. stored in the EEPROM}
 \label{tab:sernr}
\end{table}

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|c|c|c|c|c|c|}\hline
Production time & ALICE start SerNr. & ALICE end SerNr. & MSC start SerNr. & MSC end SerNr. & Mode\\\hline\hline
05.2006 & 1 & 60 & 0606620001 -2 & 0606620060 -2 & APC\\\hline
09.2006 & 101 & 170 & 0611230001 -2 & 0606620070 -2 & APC\\\hline
10.2006 & 201 & 270 & 0611240001 -2 & 0606620070 -2 & APC\\\hline
05.2007 & 300 & 369 & (produced by KK) & - & APC\\\hline
08.2007 & 370 & 1299 & (produced by KK) & - & CCC\\\hline
\end{tabular}
\caption[Production runs and serial numbers]{Production runs and serial numbers. The mode of operation is the initially
programmed one, APC means "automatic power control", CCC means "constant current
control". They will be shortly described later, for the full description refer to the LTC5100 datasheet \cite{lt-ltc}.}
 \label{tab:prodrun}
\end{table}

\subsection{Writing to the EEPROM}
\label{i2c:eep-wrprot}

In order to write to the EEPROM, the write protection signal from the CPLD should be inactive. This is only possible by
writing 11 in the \reg{SPAPAR.f}. In normal operation mode the write protection is active and prevents accidental damage
of the configuration.

\section{Laser driver chip LTC5100}
\label{i2c:ltc}

\subsection{Power-up configuration of the LTC chip}
\label{i2c:ltc-pwrup}

After power up, the LTC chip acts as I2C master and loads its configuration from the serial EEPROM. If the EEPROM is
missing or empty or I2C error occurs, the LTC tries again after 64ms.

The correspondence between the EEPROM data and the configuration registers in the LTC chip is shown in the next
table \ref{tab:eep-ltc}

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|c|l|c|c|c|}\hline
Address(LTC) & Name & Bits & Hi byte stored in EEP at addr.& Lo byte stored in EEP at addr.\\\hline\hline
0x0D & T\_EXT & 10 & - & -\\\hline
0x10 & SYS\_CONFIG & 8 & - & 0x60\\\hline
0x11 & IB\_LIMIT & 7 & - & 0x61\\\hline
0x13 & FLT\_CONFIG & 12 & 0x63 & 0x62\\\hline
0x15 & IB(IMD) & 12 & 0x65 & 0x64\\\hline
0x16 & IB\_TC1(IMD\_TC1) & 8 & - & 0x66\\\hline
0x17 & IB\_TC2(IMD\_TC2) & 8 & - & 0x67\\\hline
0x19 & IM & 12 & 0x69 & 0x68\\\hline
0x1A & IM\_TC1 & 8 & - & 0x6A\\\hline
0x1B & IM\_TC2 & 8 & - & 0x6B\\\hline
0x1D & T\_NOM & 12 & 0x6D & 0x6C\\\hline
0x1E & LOOP\_GAIN & 8 & - & 0x6E\\\hline
0x1F & PEAKING & 5 & - & 0x6F\\\hline
\end{tabular}
\caption[Configuration registers in the LTC chip and their location in the EEPROM]{Configuration registers in the LTC chip and their location in the EEPROM}
 \label{tab:eep-ltc}
\end{table}

For the full description of the LTC5100 chip please read the datasheet \cite{lt-ltc}.

\subsection{Configuration registers in the LTC chip}
\label{i2c:ltc-conf}

Here follows short description of all configuration registers in the LTC chip.

\reg{T\_EXT} - externally supplied temperature for the temperature compensation calculations. The scaling is as in T\_NOM.

\reg{SYS\_CONFIG} contains 8 single flags, for our case CCC (constant current control) mode 10010110b = {\ttfamily 0x96}.
The first ORIs were configured in APC (automatic power control) mode, in this case the value is {\ttfamily 0x9E}.
Table \ref{tab:ltc-sys-conf} shows the bitfield definitions briefly, for the full description please 
refer to Table 8 in the datasheet of the LTC chip \cite{lt-ltc}.

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|l|c|p{0.8cm}|p{1.5cm}|p{8.5cm}|}\hline
Bitfield & Bit & Reset value & Current configuration & Comment (current configuration)\\\hline\hline
Cml\_en & 7 & 0 & 1 & 0 - Floating differential termination 100 $\Omega$; 1 - CML compatible input termination 50 $\Omega$ from In+ and from In- to $V_{DD}$\\\hline
Md\_polarity & 6 & 0 & 0 & 0 - Cathode connected to MD pin; 1 - Anode connected to MD pin\\\hline
Ext\_temp\_en & 5 & 0 & 0 & 0 - Use internal temperature sensor; 1 - Externally supplied through i2c\\\hline
Power\_down\_en & 4 & 1 & 1 & 0 - No power reduction when transmitter is disables; 1 - Reduce power consumption when transmitter is disabled\\\hline
Apc\_en & 3 & 0 & 0 & 0 - Constant current control; 1 - Automatic power control using feedback from the monitor diode\\\hline
En\_polarity & 2 & 0 & 1 & 0 - Active low; 1 - Active high\\\hline
Soft\_en & 1 & 0 & 1 & 0 - Disable the transmitter; 1 - Enable the transmitter (if the EN pin is active)\\\hline
Operating\_mode & 0 & 0 & 0 & 0 - Standalone, configuration parameters are loaded from an external EEPROM; 1 - Configuration parameters are set by
an external microprocessor\\\hline
\end{tabular}
\caption[SYS\_CONFIG bitfields]{SYS\_CONFIG bitfields}
 \label{tab:ltc-sys-conf}
\end{table}

\reg{IB\_LIMIT} - Laser bias current limit.

The value \verb+Ib_limit+ is 7 bit unsigned integer. Sets the detection level for overcurrent fault. The physical bias current
limit is given by:

\begin{equation}
\label{i2c:ltc-conf:ib_limit}
  I_{B(LIMIT)} = \frac{Ib\_limit}{128} \cdot (Is\_rng + 1)\cdot 9 mA (typical)
\end{equation}

All ORIs have {\ttfamily 0x71} in this register, which corresponds to 8~mA. Note that if for some reason
\verb+Is_rng+ was changed, the physical value of $I_{B(LIMIT)}$ will be affected and should be adjusted properly.

\reg{FLT\_CONFIG} - Fault configuration. Please refer to Table 20 in the datasheet of the LTC chip \cite{lt-ltc}
for the full description. Here briefly the current configuration of the ORI boards, all have the same value in this
register - {\ttfamily 0x2C7}.

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|l|c|p{1.5cm}|p{1.5cm}|p{7.5cm}|}\hline
Bitfield & Bit & Reset value & Current configuration & Comment (current configuration)\\\hline\hline
Rep\_flt\_inhibit & 11 & 0 & 0 & allow repeated attempts to clear a fault and re-enable the transmitter\\\hline
Rapid\_restart\_en & 10 & 1 & 0 & disabled, 300ms for restart\\\hline
Flt\_drv\_mode & 9..8 & 00 & 10 & Open drain with 0.425mA pull up\\\hline
Lpc\_en & 7 & 1 & 1 & Laser power control enabled\\\hline
Auto\_shutdn\_en & 6 & 1 & 1 & Enabled, when a fault occurs, the transmitter is automatically disabled.\\\hline
Flt\_pin\_polarity & 5 & 1 & 0 & Active low: the FAULT pin is driven low to signal a fault.\\\hline
Flt\_pin\_overdrive & 4 & 0 & 0 & The FAULT pin is driven active when a fault occurs.\\\hline
Force\_flt & 3 & 0 & 0 & Force the FAULT pin inactive\\\hline
Over\_pwr\_en & 2 & 1 & 1 & Enables detection of a laser overpower fault\\\hline
Under\_pwr\_en & 1 & 1 & 1 & Enables detection of a laser underpower fault\\\hline
Over\_current\_en & 0 & 1 & 1 & Enables detection of a laser overcurrent fault\\\hline
\end{tabular}
\caption[FLT\_CONFIG bitfields]{FLT\_CONFIG bitfields}
 \label{tab:ltc-flt-conf}
\end{table}

The FAULT pin is active low, this means FAULT=1 is good, FAULT=0 is bad. See also the CPLD status registers
in \ref{j2c:cpld}.

\reg{IB(IMD)} - Laser bias current register (Monitor diode current in APC mode).

Bits 11..10 (\verb+Is_rng+) determine the source current range,
0 for 9~mA, 1 for 18~mA, 2 for 27~mA and 3 for 36~mA. We work in the first or in the second range (9~mA or 18~mA).
Even if the bias current is below~9 mA, one should switch to the next range if the sum of the bias current and the modulation
current exceeds the 9~mA limit.

Bits 9..0 (\verb+Ib_nom+) set the desired bias current (in constant current control mode) or the monitor diode current (in APC mode).
The bitfield is an unsigned 10-bit integer.
Most of the ORIs are programmed in the CCC mode, the rest (in APC mode) should be reprogrammed soon. In constant current
control (CCC) mode the bias current at temperature \verb+T_nom+ is given by:

\begin{equation}
\label{i2c:ltc-conf:ltc_ib}
  I_{B} = \frac{Ib\_nom}{1024} \cdot (Is\_rng + 1)\cdot 9mA (typical)
\end{equation}

This current is set individually on each ORI board in order to achieve the desired optical power.

\reg{IB\_TC1(IMD\_TC1)} - Laser bias/Modulation current first order temperature coefficient. We make only a linear compensation and
use the value of 8.

\reg{IB\_TC2(IMD\_TC2)} - Laser bias/Modulation current second order temperature coefficient. We make only a linear compensation and
use the default (reset) value 0.

\begin{figure}[htb]
 \centering
 \includegraphics*[width=12cm]{chap_i2c/ori_ibias.eps}
 \caption[The dependence of the optical power on the bias current]{The dependence of the optical power on the bias current}
 \label{fig:ibias}
\end{figure}

\reg{IM} - Laser modulation current.

Bits 11..10 (\verb+Im_rng+) determine the modulation current range,
0 for 4.5~mA, 1 for 9~mA, 2 for 13.5~mA and 3 for 18~mA.
Note that this is the mean modulation current, the peak-to-peak values are twice larger.

Bits 9..0 (\verb+Im_nom+) determine the modulation current at the nominal temperature. The bitfield is an unsigned 10-bit integer.
but the chip internally expects a 9 bit value from 0 to 511.
The physical modulation current at the pins of the LTC chip is given by:

\begin{equation}
\label{i2c:ltc-conf:ltc_im}
  I_{M} = \frac{Im\_nom}{512} \cdot (Im\_rng + 1)\cdot 4.5 mA (typical)
\end{equation}

Be careful, the datasheet \cite{lt-ltc} is confusing at this place. The modulation current set
here is not peak to peak, but the average current.
This current is set individually on each ORI board. Note that there is an termination resistor
between the SRC pin of the LTC chip and the anode of the laser diode. The equivalent circuit is
shown on fig. \ref{fig:rdyn}. Actually the LTC chip has one static current generator for the source current and
a fast switching current sink for modulation. When the modulation current is on, the resulting current is used to
transmit logic 0. When the modulation current is off, the resulting current is used to transmit logic 1. The number of
zeroes and ones is balanced, so the mean current though the diode is the difference between the source current and the
half of the modulation current (called average modulation current).

\begin{figure}[htb]
 \centering
 \includegraphics*[width=12cm]{chap_i2c/ori_rdyn.eps}
 \caption[The dynamical resistance of the laser diode]{The dynamical resistance of the laser diode}
 \label{fig:rdyn}
\end{figure}

The actual modulation current in the laser diode is:

\begin{equation}
\label{i2c:ltc-conf:ltc_rdyn}
  I_{MOD} = \frac{R_{TERM}}{(R_{TERM}+R_{DYN})} \cdot I_M
\end{equation}

The fig. \ref{fig:rdyn} shows a typical dependence of the laser diode voltage on
the current through the diode. The $R_{TERM}$ is 50 $\Omega$, which leads to an attenuation factor of about
0.4. However this dynamical resistance is not the same for all ORIs.

\reg{IM\_TC1} - First order temperature coefficient for modulation current. We make only a linear compensation and
use the value of 4.

\reg{IM\_TC2} - Second order temperature coefficient for modulation current. We make only a linear compensation and
use the default (reset) value 0.

\reg{T\_NOM} - Nominal temperature (includes \verb+Imd_rng+).

Bits 11..10 (\verb+Imd_rng+) determine the monitor diode current range.

\begin{table}[htb]
 \centering
  \scriptsize
\begin{tabular}{|c|c|c|}\hline
Decimal value & Monitor Diode min current ($\mu$A) & Monitor Diode max current ($\mu$A)\\\hline\hline
0 & 4.25 & 34\\\hline
1 & 17 & 136\\\hline
2 & 68 & 544\\\hline
3 & 272 & 2176\\\hline
\end{tabular}
\caption[Monitor diode current range in T\_NOM.Imd\_rng]{Monitor diode current range in T\_NOM.Imd\_rng}
\label{tab:ltc_Imd_rng}
\end{table}

The photocurrent for the same optical power is widely spread, therefore working in only one range is not possible.
Most of the ORIs have range 2, the rest have range 1. Note that this setting is essential for the APC mode, otherwise the
feedback will not work and the LTC will go to FAULT state. In CCC mode it is still nice to have the proper range
programmed in order to read back the photocurrent for diagnostics.

Bits 9..0 (\verb+T_nom+) is the nominal temperature, with respect to which all temperature compensations are made.

\begin{equation}
  T\_nom = (T+273^0C)/0.5^0C,
\end{equation}

where $T$ is the nominal temperature in degrees Celsius.

Note that \verb+T_nom+ is used only if some of the temperature coefficients are different from 0. The chip has an internal
temperature sensor, but can be programmed to use an external sensor. In this case the temperature has to be regularly
written to the \reg{T\_EXT} register.

All ORIs have {\ttfamily 0x272} as \verb+T_nom+, which corresponds to $40^0C$.

\reg{LOOP\_GAIN} - Bias current loop gain. We use the default (reset) value {\ttfamily 00100001b = 0x21}.

\reg{PEAKING} - High speed modulation peaking. We use the default (reset) value {\ttfamily 10000b = 0x10}.

\subsection{Status and DAC registers in the LTC chip}
\label{i2c:ltc-stat}

The status and DAC registers in the LTC chip are summarized in the next table. Some of the DAC registers are in
generally read-write, but for the current ORI configuration they are read only.

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|c|l|c|}\hline
Address(LTC) & Name & Bits\\\hline\hline
0x01 & IS\_DAC & 10\\\hline
0x02 & IM\_DAC & 10\\\hline
0x03 & PWR\_LIMIT\_DAC & 10\\\hline
0x12 & FLT\_STATUS & 11\\\hline
 \end{tabular}
\caption[Status and DAC registers in the LTC chip]{Status and DAC registers in the LTC chip}
\label{tab:ltc_sta_dac}
\end{table}

\reg{IS\_DAC} - Source current DAC (Address 0x01). DAC setting for the source current. Read access to this DAC is
always available. Write access is only if \reg{FLT\_CONFIG}\verb+.Lpc_en+ is 0. For our configuration
this is a read only status register. The source current is given by:

\begin{equation}
\label{i2c:ltc-conf:ltc_is_dac}
  I_{S} = \frac{Is\_dac}{1024} \cdot (Is\_rng + 1)\cdot 9 mA (typical)
\end{equation}

\reg{IM\_DAC} - Modulation current DAC (Address 0x02). DAC setting for the peak-to-peak modulation current. Read
access to this DAC is always possible. Write access is only if \reg{FLT\_CONFIG}\verb+.Lpc_en+ is 0. For our configuration
this is a read only status register. The modulation current is given by:

\begin{equation}
\label{i2c:ltc-conf:ltc_im_dac}
  I_{M} = \frac{Im\_dac}{1024} \cdot (Im\_rng + 1)\cdot 9 mA (typical)
\end{equation}

\reg{PWR\_LIMIT\_DAC} - Optical power limit DAC (read only at 0x03). In the CCC mode this register has no function.


\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|l|c|p{1.5cm}|p{1.5cm}|p{7cm}|}\hline
Bitfield & Bit & Reset value & Current configuration & Comment (current configuration)\\\hline\hline
Transmit\_ready & 10 & 0 & - & 0: Not ready, 1:Ready to transmit data\\\hline
Transmitter\_enabled & 9 & 0 & 1 & 0:Transmitter is disabled, 1:Transmitter is enabled\\\hline
En\_pin\_state & 8 & - & 1 & The EN pin of the LTC chip is 1 always when the LTC chip is powered\\\hline
Faulted\_twice & 7 & 0 & - & Only active when Rep\_flt inhibit is set\\\hline
Faulted\_onece & 6 & 1 & - & Only active when Rep\_flt inhibit is set\\\hline
Faulted & 5 & 1 & 0 & 0:The LTC5100 is not in Faulted state, 1:A Fault has occurred and the LTC5100 has entered
the Faulted state\\\hline
Under\_voltage & 4 & 1 & - & Indicates that a power supply undervoltage event occurred. 0:No Fault, 1:Fault
detected. The Undervoltage bit is always set at power up, READ the \reg{FLT\_STATUS} register after power-up to clear this bit\\\hline
Mem\_load\_error & 3 & 0 & 0 & Indicates that an attempt to load the register from EEPROM was started but did
not complete successfully. 0: No Fault, 1:EEPROM load faulted. READ the
\reg{FLT\_STATUS} register after power-up to clear this bit\\\hline
Over\_power & 2 & 0 & 0 & Can happen only in APC mode\\\hline
Under\_power & 1 & 0 & 0 & Can happen only in APC mode\\\hline
Over\_current & 0 & 0 & 0 & Indicates that the laser bias current exceeds the value set in the IB\_LIMIT
register. READ the \reg{FLT\_STATUS} register to clear this bit\\\hline
\end{tabular}
\caption[FLT\_STATUS bitfields]{FLT\_STATUS bitfields}
 \label{tab:ltc-flt-status}
\end{table}


\subsection{ADCs in the LTC chip}
\label{i2c:ltc-adcs}

For the normal operation of the LTC chip, the temperature and some currents are digitized by the internal ADCs
and updated regularly - the chip temperature, the modulation current and the source current (in CCC mode).
For diagnostics some additional measurements can be done by the user ADC in the chip. Actually the only
important current which can be measured by the user ADC is the monitor current as it is proportional to the
optical power.

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|c|l|c|p{8cm}|}\hline
Address(LTC) & Name & Bits & Comment\\\hline\hline
0x05 & T\_INT\_ADC & 10 & Internal temperature\\\hline
0x06 & IM\_ADC & 10 & Modulation current\\\hline
0x07 & IS\_ADC(IMD\_ADC) & 10 & Source current (CCC mode) or Monitor diode current (APC mode)\\\hline
0x18 & USER\_ADC & 3 & Writing: select between 0: Source current, 1: Modulation current, 2: Laser diode
voltage, 3: Monitor diode current, 4: Temperature, 5: Termination resistor voltage\\\hline
0x18 & USER\_ADC & 15 & Bits 14..12 show the selected source (see above), Bit 10 is Valid and is 1 if the ADC
has finished the conversion and the result is valid, Bits 9..0 represent the result of the conversion\\\hline
\end{tabular}
\caption[ADC registers in the LTC chip]{ADC registers in the LTC chip}
 \label{tab:ltc_adc}
\end{table}

\reg{T\_INT\_ADC} - The temperature in $^0C$ is given by:

\begin{equation}
  T = T\_int\_adc \cdot 0.5^0C-273^0C
\end{equation}

\reg{IM\_ADC} - This register contains the last conversion of the average modulation current at the pins of the LTC
chip. The peak-to-peak current is twice the average current. Note that the full range of the ADC is not utilized
here, the expected ADC code is from 0 to 511.

\begin{equation}
%\label{i2c:ltc-conf:ltc_im_dac}
  I_{M} = \frac{Im\_adc}{512} \cdot (Im\_rng + 1)\cdot 4.5 mA (typical)
\end{equation}

\reg{IS\_ADC} - In CCC mode here is the last conversion of the source current.

\begin{equation}
%\label{i2c:ltc-conf:ltc_im_dac}
  I_{S} = \frac{Is\_adc}{1024} \cdot (Is\_rng + 1)\cdot 9 mA (typical)
\end{equation}

Note that the bias current can not be measured directly, it is simply the difference between the measured source
and modulation currents:

\begin{equation}
\label{i2c:ltc-conf:ibias_meas}
  I_{B} = I_{S}(ADC) - I_{M}(ADC)
\end{equation}


USER\_ADC - in order to use it, first write the selected channel, wait at least 4 ms, then read back the result.
The interpretation of the $I_S$, $I_M$ and the temperature is like in case of the 
\reg{IS\_ADC}, \reg{IM\_ADC} and \reg{T\_INT\_ADC} registers. Here only the calculation of the rest.

2: Laser diode voltage $V_{LD}$

\begin{equation}
  V_{LD} = \frac{ADC\_code}{1024} \cdot 3.5 V
\end{equation}

3: Monitor diode current $I_{MD}$

\begin{equation}
  I_{MD} =  4.25 \mu A \cdot 4^{Imd\_rng} \cdot exp(ln(8) \cdot \frac{ADC\_code}{1024})
\end{equation}

5: Termination resistor voltage $V_{TERM}$

\begin{equation}
  V_{TERM} = \frac{ADC\_code}{1024} \cdot (Is\_rng + 1) \cdot 400 mV
\end{equation}

From this voltage one can easy calculate the termination resistor:

\begin{equation}
\label{i2c:ltc-conf:rterm}
  R_{TERM} = \frac{V_{TERM}}{I_{S}}
\end{equation}

The expected value is about 50~$\Omega$.

