%  svn Id  : $Id$
\chapter{Appendix}
\label{app}

\section{CPLD pinout}
\label{app:cpld}

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|p{3cm}|c|l|p{7cm}|}\hline
Pin & Signal Type & Signal Name & Comment\\\hline\hline

66 & Input & clk & 125 MHz clock from the high quality quartz\\\hline

100 & Input & RESET\_n & global reset, active low\\\hline
99 & Input & DIS\_JTG & 1 - disable JTAG and j2c, 0 - disable i2c\\\hline

20, 19, 17, 16, 15, 14, 11, 10, 9, 8 & Input & NI\_D[0..9] &  parallel input data port\\\hline
6 & Input & NI\_STR & strobe of the parallel input data port\\\hline
5 & Input & NI\_CTL & unused here\\\hline

38 & Input & jTCK & j2c clock\\\hline
88 & Input & jTDI & j2c serial data input\\\hline
21 & Tri-Out & jTDO & j2c serial data output\\\hline
87 & Input & jTMS & j2c strobe\\\hline

86 & Output & WP\_EEP & EEPROM write protection, 1 - disable writing, 0 - enable writing, see command 11 in table \ref{tab:ori_mode}\\\hline
84 & Output & EN & EN pin of the LTC5100 chip = SD2ANL\\\hline
81 & Input & FAULT & FAULT pin of the LTC5100 chip\\\hline
97 & Bidir & SDA & i2c serial data of the LTC and EEPROM\\\hline
98 & Tri-Out & SCL & i2c serial clock of the LTC and EEPROM\\\hline

3 & Output & SD2ANL & enable for the voltage regulators 2.5V(TLK) and 3.3V(LTC), see command 14 in table \ref{tab:ori_mode}\\\hline

47 & Output & PRBSEN & TLK: enable the pseudorandom generator, see command 10 in table \ref{tab:ori_mode}\\\hline
49 & Output & ENABLE & TLK: = SD2ANL\\\hline
48 & Output & LCKREFN & TLK: low\\\hline
53 & Output & LOOPEN & TLK: low\\\hline
44 & Output & TESTEN & TLK: low \\\hline
50 & Output & TX\_ER & TLK: low\\\hline

54 & Output & TX\_EN & TLK: data valid\\\hline
80, 79, 78, 72, 71, 70, 69, 67, 65, 64, 61, 60, 59, 58, 56, 55 & Output & TXD[0..15] & TLK: parallel data intput\\\hline

24 & Input & TCK & CPLD JTAG port\\\hline
2 & Input & TDI & CPLD JTAG port\\\hline
74 &  Tri-Out & TDO & CPLD JTAG port\\\hline
52 & Input & TMS & CPLD JTAG port\\\hline

25, 40, 75, 90 & Pwr-Gnd & VCC & core voltage (the CPLD has internal voltage regulator) = 3.3V\\\hline
13, 95, 33 & Pwr-Gnd & VCCIO0 & I/O voltage = 3.3V\\\hline
45, 63, 83 & Pwr-Gnd & VCCIO1 & I/O voltage = 3.3V\\\hline

1, 26, 51, 76 & Pwr-Gnd & GND & GND core\\\hline
7, 18, 32, 96 & Pwr-Gnd & GNDIO0 & GND I/O\\\hline
46, 57, 68, 82 & Pwr-Gnd & GNDIO1 & GND I/O\\\hline
\end{tabular}
\caption[CPLD pinout]{CPLD pinout}
\label{tab:app_cpld_pins}
\end{table}

%-----------------------------------------------------------------------------

%\newpage


\section{Schematics and Layout}
\label{app:sch}

Here is the complete schematics of the ORI board. All components without value or with the remark "nicht best\"ucken"
are not soldered.

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_appendix/sch1.eps}
 \caption[Schematics: Connectors, LVDS to TTL, CPLD input]{Schematics: Connectors, LVDS to TTL, CPLD input}
 \label{fig:sch1}
\end{figure}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_appendix/sch2.eps}
 \caption[Schematics: SerDes, CPLD, Qgen]{Schematics: SerDes, CPLD, Qgen}
 \label{fig:sch2}
\end{figure}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_appendix/sch3.eps}
 \caption[Schematics: CPLD power pins]{Schematics: CPLD power pins}
 \label{fig:sch3}
\end{figure}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=14cm]{chap_appendix/sch4.eps}
 \caption[Schematics: Optocouplers]{Schematics: Optocouplers}
 \label{fig:sch4}
\end{figure}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_appendix/sch5.eps}
 \caption[Schematics: Laser driver and EERPOM]{Schematics: Laser driver and EERPOM}
 \label{fig:sch5}
\end{figure}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=14cm]{chap_appendix/sch6.eps}
 \caption[Schematics: Voltage regulators]{Schematics: Voltage regulators}
 \label{fig:sch6}
\end{figure}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_appendix/components.eps}
 \caption[PCB: Top and bottom components]{PCB: Top and bottom components}
 \label{fig:pcb-cmp}
\end{figure}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_appendix/layout.eps}
 \caption[PCB: Top and bottom layout]{PCB: Top and bottom layout}
 \label{fig:pcb-lay}
\end{figure}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_appendix/photo.eps}
 \caption[PCB: Top and bottom]{PCB: Top and bottom}
 \label{fig:pcb-photo}
\end{figure}

%-----------------------------------------------------------------------------
