`timescale 1 ns/1 ns

module TestBench();

	wire BC;
	BC_clk slow(BC);

	wire clk;
	FastClk fast(clk);

	reg reset;
	reg input1;
	reg input2;

	wire output1;
	wire output2;
	wire [1:0] phase;

	SynchrInp syn(
		.clk(clk),
		.reset(reset),
		.inp1(input1),
		.inp2(input2),
		.outp1(output1),
		.outp2(output2),
		.mon_phase(phase));

	task pulse1;
	begin
		@(posedge clk)input1 <= 1;
		#25 input1 <= 0;
	end
	endtask	
	
	task pulse2;
	begin
		@(posedge clk)input2 <= 1;
		#25 input2 <= 0;
	end
	endtask	

	integer i;	

	initial
	begin
		reset <= 1;
		input1 <= 0;
		input2 <= 0;
		
		@(posedge BC);
		@(posedge BC) reset <= 0;
	
		$display("##################################");
		$display("## Inp1 & Inp2 near each other ###");
		$display("##################################");
		#100;
		pulse1();
		pulse2();
		for (i = 0; i<50; i=i+1)
		begin
			#100;
			pulse1();
			repeat (i) #1;
			pulse2();
		end

		$display("##################################");
		$display("############# Aligned ############");
		$display("##################################");
		for (i=0; i<4; i=i+1)
		begin
			repeat(i) @(posedge clk)
			repeat(100)
			begin	
				pulse1();
				#50 pulse2();
				#150;
			end
		end
		$display("##################################");
		$display("######### not Aligned ############");
		$display("##################################");
		repeat(100)
		begin	
			pulse1();
			#37 pulse2();
			#113;
		end
	end
endmodule