`timescale 1 ns/1 ns

module TestBench();

	wire 
		clk,
		reset,
		LM,
		LM_SA;
	
	wire [5:0] mon_state_seqGen;
	wire [31:0] rnd;

	reg
		enable,
		pulser,
		BUSY_GTU;

	reg [1:0] mode;
	reg [7:0] seqGen_LMSA;
	reg [16:0] seqGen_freq;
	reg [31:0] seqGen_threshold;	
	

	SequenceGen seqGen(
		.clk(clk),
		.enable(enable),
		.pulser(pulser),
		.mode(mode),
		.BUSY_GTU(BUSY_GTU),
		.seqGen_LMSA(seqGen_LMSA),
		.seqGen_freq(seqGen_freq),
		.seqGen_threshold(seqGen_threshold),
		.reset(reset),
		.LM(LM),
		.LM_SA(LM_SA),
		.rnd(rnd),
		.mon_state_seqGen(mon_state_seqGen));

	
	BC_clk bc(clk);

	initial
	begin
		enable <= 0;
		pulser <= 0;
		BUSY_GTU <= 0;
		mode <= 0;
		seqGen_LMSA <= 0;
		seqGen_freq <= 0;
		seqGen_threshold <= 0;

		#100;
		seqGen_LMSA <= 8'b0010_1011;	// 43
		seqGen_freq <= 17'b0_0000_1111_1001_1110 - seqGen_LMSA; // -2 !! not -1
		seqGen_threshold <= 32'b1000_0000_0000_0000_0000_0000_0000_0000;

		#100;
		enable <= 1;
		mode <= 2'b11;

		@(posedge LM_SA) #125 BUSY_GTU <= 1;
		#400 BUSY_GTU <= 0;
		#100000;
		
		#100;
		enable <= 1;
		mode <= 2'b10;
		
		#10000;
		enable <= 0;	

		#100;
		enable <= 1;
		mode <= 2'b01;
	
		#500;
		mode <= 2'b10;

		#10000
		enable <= 0;
		seqGen_freq <= 17'b0_0000_0000_0000_0111;
		#100 enable <= 1;
		@(posedge LM_SA) #125; #150 //BUSY_GTU <= 1;
		#300 BUSY_GTU <= 0;
	
		@(posedge LM_SA) #125; #100 BUSY_GTU <= 1;
		#300 BUSY_GTU <= 0;
 
		@(posedge LM_SA) #125; #110 BUSY_GTU <= 1;
		#300 BUSY_GTU <= 0;
 
		@(posedge LM_SA) #125; #120 BUSY_GTU <= 1;
		#300 BUSY_GTU <= 0;
 
		@(posedge LM_SA) #125; #130 BUSY_GTU <= 1;
		#300 BUSY_GTU <= 0;
 
		@(posedge LM_SA) #125; #140 BUSY_GTU <= 1;
		#300 BUSY_GTU <= 0;
 
		@(posedge LM_SA) #125; #150 BUSY_GTU <= 1;
		#300 BUSY_GTU <= 0;
 
		@(posedge LM_SA) #125; #160 BUSY_GTU <= 1;
		#300 BUSY_GTU <= 0;
 
		@(posedge LM_SA) #125; #170 BUSY_GTU <= 1;
		#300 BUSY_GTU <= 0;

		#10000;		
	end
endmodule