`timescale 1 ns/1 ns


module TestBench();

	wire clk;

	BC_clk bc(clk);

	reg inp;
	wire [31:0] rate;

	rateMonitor rm(
		.clk(clk),
		.toMonitor(inp),
		.rate(rate));

	wire [31:0] rnd;

	MersenneTwister_TT800 mt(
		.clk(clk),
		.rnd(rnd));
	
	reg random;

	parameter threshold = 32'd4_200_000_000;	

	initial
	begin
		inp <= 0;
		random <= 0;

		repeat (100)
		begin
			inp <= 1;
			#25
			inp <= 0;
			#150;
		end

		#1000;
		repeat (100)
		begin
			inp <= 1;
			#50
			inp <= 0;
			#150;
		end

		#1000 random <= 1;
	end

	always @(posedge clk)
	begin
		if (random)
		begin
			inp <= 0;
			
			if (rnd > threshold)
			begin
				inp <= 1;
			end
		end
	end
endmodule