`timescale 1 ns/1 ns

module TestBench();
	
	wire clk_BC;
	wire clk_BC_shifted;
	reg reset;
	reg LM_GL;
	reg TTC_A;
	reg BUSY_GTU;
	reg [5:0] LMtoL0min;
	reg [5:0] LMtoL0max;
	reg [5:0] LMtoL0delay;
	reg [6:0] LMtoL0rec;
	reg [8:0] LMtoL1min;
	reg [8:0] LMtoL1max;
	reg [8:0] LMtoL1delay;
	reg [8:0] LMtoL1rec;
	reg [8:0] LMtoL1acc;
	
	wire LM;
	wire L0;
	wire L1;
	wire busy;
	wire [3:0] state_mon;

	reg TTCtrd_A;

	integer i;

	BC_clk slow(clk_BC);
	BC_clk_shifted shifted(clk_BC_shifted);

	Protocol_conv pc(
		.clk(clk_BC_shifted),
		.reset(reset),
		.LM_GL(LM_GL),
		.TTC_A(TTC_A),
		.BUSY_GTU(BUSY_GTU),
		.LMtoL0min(LMtoL0min),
		.LMtoL0max(LMtoL0max),
		.LMtoL0delay(LMtoL0delay),
		.LMtoL0rec(LMtoL0rec),
		.LMtoL1min(LMtoL1min),
		.LMtoL1max(LMtoL1max),
		.LMtoL1delay(LMtoL1delay),
		.LMtoL1rec(LMtoL1rec),
		.LMtoL1acc(LMtoL1acc),
		.busy(busy),
		.LM(LM),
		.L0(L0),
		.L1(L1),
		.state_mon(state_mon));


	initial
	begin
		TTCtrd_A <= 0;
		reset <= 0;
		LM_GL <= 0;
		TTC_A <= 0;
		BUSY_GTU <= 0;
		LMtoL0min = 6'd44;
		LMtoL0max = LMtoL0min + 6'd2 + 6'd1;
		LMtoL0delay = LMtoL0min + 1'd1;
		LMtoL0rec = 6'd63;
		LMtoL1min = 9'd305;
		LMtoL1max = LMtoL1min + 9'd2 + 9'd1;
		LMtoL1delay = LMtoL1min + 9'd5;
		LMtoL1rec = 9'd350;
		LMtoL1acc = 9'd320;
	
		
		#100;
/*
		$display("#########################################");
		$display("%tns: Complete Sequence",$time/1000.0);
		$display("#########################################\n");
		#100;
		@(posedge clk_BC) LM_GL <= 1;
		#25	LM_GL <= 0;

		#1125	TTC_A <= 1;
		#25	TTC_A <= 0;

		#6275	BUSY_GTU <= 1;
		#200	TTC_A <= 1;
		#50	TTC_A <= 0;
		#1000	BUSY_GTU <= 0;


		#1000;	
		$display("#########################################");
		$display("%tns: Without L1",$time/1000.0);
		$display("#########################################\n");
		#100;
		@(posedge clk_BC) LM_GL <= 1;
		#25	LM_GL <= 0;

		#1125	TTC_A <= 1;
		#25	TTC_A <= 0;

		#6275	BUSY_GTU <= 1;
		#1000	BUSY_GTU <= 0;

		#1000;	

		$display("#########################################");
		$display("%tns: Without L0",$time/1000.0);
		$display("#########################################\n");
		#100;
		@(posedge clk_BC) LM_GL <= 1;
		#25	LM_GL <= 0;

		#2000;	

		#1000;
		$display("#########################################");
		$display("%tns: Variation of L1 arrival",$time/1000.0);
		$display("#########################################\n");
		for (i=0; i<=6; i=i+1)
		begin

			$display("###############################");
			$display("%tns: %d",$time/1000.0,i);
			$display("###############################\n");
	
			#100;
				@(posedge clk_BC) LM_GL <= 1;
			#25 	LM_GL <= 0;
	
			#1125 	TTC_A <= 1;
			#25 	TTC_A <= 0;
	
			#6275	BUSY_GTU <= 1;
			#145;
			repeat (i) #25;
				@(posedge clk_BC) TTC_A <= 1;
			#50	TTC_A <= 0;
			#1000	BUSY_GTU <= 0;		
			#1000;
		end

*/
		#1000;	
		$display("#########################################");
		$display("%tns: Variation of L0 arrival",$time/1000.0);
		$display("#########################################\n");
		for (i=0; i<=6; i=i+1)
		begin

			$display("###############################");
			$display("%tns: %d",$time/1000.0,i);
			$display("###############################\n");
	
			#100;
				@(posedge clk_BC) LM_GL <= 1;
			#25 	LM_GL <= 0;
	
			#1070
			repeat (i) #25;
 				@(posedge clk_BC) TTC_A <= 1;
			#25 	TTC_A <= 0;			
	
			#8000;
		end

	end

	always @(posedge clk_BC)
	begin
		TTCtrd_A <= LM || L0 || L1;
	end
endmodule