`timescale 1 ns/1 ns

module TestBench();

	wire DL_BC;
        BC_clk bc(DL_BC);
	
	reg start;
	reg SSM_read;
	reg [1:0] SSM_mode;
	reg [31:0] count_BC;
        reg [4:0] mon_state_PC;
        reg [5:0] mon_state_seqGen;
        reg [1:0] mon_phase;
	
	wire SSM_CLK;
	wire SSM_CE;
	wire SSM_WRITE;
	wire [17:0] SSM_data;
	wire [19:0] SSM_A;
	wire SSM_busy;
	
	wire [17:0] SSM_DQ;
	reg [17:0] SSM_DQ_data;
	assign SSM_DQ = SSM_WRITE ? SSM_DQ_data : 18'bz;
	reg [17:0] data;
	reg write_en;

	SSMcontroler ssm(
        	.clk(DL_BC),
        	.start(start),
        	.SSM_read(SSM_read),
        	.SSM_mode(SSM_mode),
		.count_BC(count_BC),
		.mon_state_PC(mon_state_PC),
		.mon_state_seqGen(mon_state_seqGen),
		.mon_phase(mon_phase),
        	.SSM_CLK(SSM_CLK),
        	.SSM_CE(SSM_CE),
        	.SSM_WRITE(SSM_WRITE),
		.SSM_A(SSM_A),
        	.SSM_data(SSM_data),
        	.SSM_busy(SSM_busy),
        	.SSM_DQ(SSM_DQ));
	
	reg write;
	reg read;

	initial
	begin
		start <= 0;
		SSM_read <= 0;
		SSM_mode <= 0;
		SSM_DQ_data <= 0;
		count_BC <= 0;
		mon_state_PC <= 5'b0_1010;
		mon_state_seqGen <= 6'b01_0101;
		mon_phase <= 2'b11;
		data <= 0;
		write_en <= 0;
		
		write <= 0;
		read <= 0;	

		#50 SSM_mode <= 2'b01;

		#200 write <= 1;
		$display("%tns: start writing.",$time/1000.0);
		#200 write <= 0;
		#200 write <= 1;
		$display("%tns: start writing.",$time/1000.0);
		#200 write <= 0;

		#27000000;
		$display("%tns: done with writing.",$time/1000.0);
		#100;
		$display("%tns: start reading.",$time/1000.0);
		repeat (1000)
		begin
			#200 read <= 1;
			#100 read <=0;
		end
	end

	always @(posedge DL_BC)
	begin
		count_BC <= count_BC + 1'b1;
		
		start <= 0;
		if (write == 1)
		begin
			if (!SSM_busy)
			begin
				SSM_read <= 0;
				start <= 1;
			end
			else
			begin	
				start <= 0;
			end
		end

		if (read == 1)
		begin
			//if (!SSM_busy)
			//begin
				start <= 1;
				SSM_read <= 1;
			//end
			//else
			//begin
				data[17:0] <= SSM_data;
				write_en <= 1;
			//end
		end

		
		if (SSM_A[0] == 0)	SSM_DQ_data <= 18'b10_1010_1010_1010_1010;
		else			SSM_DQ_data <= 18'b01_0101_0101_0101_0101;
	
		if (SSM_A == 20'b0000_0000_0000_0000_0000) SSM_DQ_data <= 18'b11_1111_1111_1111_1111;
		if (SSM_A == 20'b1111_1111_1111_1111_1111) SSM_DQ_data <= 0;
		
//		SSM_DQ_data <= SSM_A[17:0];
	end

endmodule