`timescale 1 ns/1 ns

module TestBench();

	wire DL_BC;
        BC_clk bc(DL_BC);

	reg ptcom_en;
	reg [2:0] ptcom_code;
	wire ptcom_seq;
	wire ptcom_reset;
	wire ptcom_busy;

        PTcommands pt(
                .clk(DL_BC),
                .enable(ptcom_en),
                .code(ptcom_code),
                .PTsequence(ptcom_seq),
                .reset(ptcom_reset),
		.PTsending(ptcom_busy));

	initial
	begin
		ptcom_en <= 0;
		ptcom_code <= 0;

		#1000;
		ptcom_en <= 1;
		ptcom_code <= 3'b001;
		#25 ptcom_en <= 0;

		#1000;
		ptcom_en <= 1;
		ptcom_code <= 3'b010;
		#25 ptcom_en <= 0;

		#1000;
		ptcom_en <= 1;
		ptcom_code <= 3'b011;
		#25 ptcom_en <= 0;

		#1000;
		ptcom_en <= 1;
		ptcom_code <= 3'b100;
		#25 ptcom_en <= 0;

		#1000;
		ptcom_en <= 1;
		ptcom_code <= 3'b101;
		#25 ptcom_en <= 0;

		#1000;
		ptcom_en <= 1;
		ptcom_code <= 3'b110;
		#25 ptcom_en <= 0;

		#1000;
		ptcom_en <= 1;
		ptcom_code <= 3'b111;
		#25 ptcom_en <= 0;

//		#1000 $finish;
	end
endmodule