`timescale 1 ns/1 ns

module TestBench();

	parameter
		reset_LTU 	= 16'b1000_0000_0000_0000,
		enable_seq 	= 16'b0100_0000_0000_0000,
		mode_pulser	= 16'b0001_0000_0000_0000,
		mode_BC		= 16'b0010_0000_0000_0000,
		mode_rnd	= 16'b0011_0000_0000_0000;
	
	integer i;
	integer time_1;
	integer time_2;
	
	reg CON_SPARE1; 	// CTP_ORBIT;
	reg CON_SPARE2;	// CTP_PREPULSE;
	reg CON_SPARE3;	// CTP_L0;
	reg CON_SPARE4;	// CTP_L1;
	reg TTC_B;		// CTP_L1Data;
	wire TTC_A;		// CTP_L2STROBE;
	wire LM_GL;		// CTP_L2DATA;
//		Double coaxial connectors
	wire OUT_A;
	wire OUT_B;
	reg IN_PULSER;
	wire OUT_L1;
	reg IN_SPARE;		// IN or OUT
	wire OUT_SPARE;	//
	wire OUT_ORBIT;
	wire OUT_PREPULSE;
//		Lemo PCB connectors
	wire OUT_1L0;
	wire OUT_2L0;
	wire OUT_3L0; 	// OUT_3L0 or IN_LVDS
	reg IN_LVDS;		//
	wire OUT_BUSY;
	wire IN_BUSY1;
	reg IN_BUSY2;
//		LEDs
	wire LED_RD;
	wire LED_WR;
	wire LED_A;
	wire LED_B;
	wire LED_PLSR;
	wire LED_L1;
	wire LED_SPARE;
	wire LED_ORBIT;
	wire LED_BC;
	wire LED_PP;
	wire LED_BUSY;
	wire LED_L0;
// Clock
	wire DL_BC;
	wire [4:0] BC_DELAY;
	wire LED_LOCK;
// Test PINs
	wire TEST_C1;
	wire TEST_C2;
	wire TEST_C3;
	wire TEST_C4;
	wire TEST_C5;
	wire TEST_C6;
	wire TEST_C7;
	wire TEST_C8;
// Logic Analyzer
	wire LA_CLOCK;
	wire LA_C3_6;
	wire LA_A2_0;
	wire LA_A3_7;
	wire LA_C3_7;
	wire LA_A3_6;
	wire LA_C3_5;
	wire LA_A3_4;
	wire LA_A3_3;
	wire LA_C3_4;
	wire LA_A3_2;
	wire LA_A3_1;
	wire LA_A2_6;
	wire LA_A2_7;
	wire LA_A3_0;
	wire LA_A2_5;
	wire LA_A2_4;
	wire LA_A2_1;
	wire LA_A2_2;
	wire LA_A2_3;
	wire LA_A3_5;
// SNAP-SHOT MEMORY
	wire SSH_CLK;
	wire [19:0] SSH_A;
	wire SSH_CE;
	wire SSH_WRITE;
	wire [17:0] SSH_DQ;
// FPGA configuring
	wire INIT_DONE;
// ADC
	wire ADC_IN;
	wire ADC_CS;
	wire ADC_CLK;
	wire ADC_SDATA;
// VME J2
	wire BP_L1;
	wire BP_ORBIT;
	wire OBP_BC;
	wire BP_L1_DATA;
	wire BP_L2_STROBE;
	wire BP_L0;
	wire BP_PREPULSE;
	wire BP_L2_DATA;
	wire [31:0] D;
// VME FPGA
        reg [9:0] ADD;
        wire SPARE_1;
        wire SPARE_2;
        wire SPARE_3;
        wire SPARE_4;
        wire WRITE;
        reg MRESET;
        wire DWB;
        reg STROBE;
        reg MSTROBE;
        reg VME_CLK;
	
	BC_clk bc(clk_BC);		
	
	LTU_T ltut(
			.CON_SPARE1(CON_SPARE1), 	// CTP_ORBIT,
			.CON_SPARE2(CON_SPARE2),	// CTP_PREPULSE,
			.CON_SPARE3(CON_SPARE3),	// CTP_L0,
			.CON_SPARE4(CON_SPARE4),	// CTP_L1,
			.TTC_B(TTC_B),		// CTP_L1Data,
			.TTC_A(TTC_A),		// CTP_L2STROBE,
			.LM_GL(LM_GL),		// CTP_L2DATA,
		//		Double coaxial connectors
			.OUT_A(OUT_A),
			.OUT_B(OUT_B),
			.IN_PULSER(IN_PULSER),
			.OUT_L1(OUT_L1),
			.IN_SPARE(IN_SPARE),		// IN or OUT
			.OUT_SPARE(OUT_SPARE),	//
			.OUT_ORBIT(OUT_ORBIT),
			.IN_BC(clk_BC),
			.OUT_PREPULSE(OUT_PREPULSE),
		//		Lemo PCB connectors
			.OUT_1L0(OUT_1L0),
			.OUT_2L0(OUT_2L0),
			.OUT_3L0(OUT_3L0), 	// OUT_3L0 or IN_LVDS
			.IN_LVDS(IN_LVDS),		//
			.OUT_BUSY(OUT_BUSY),
			.IN_BUSY1(IN_BUSY1),
			.IN_BUSY2(IN_BUSY2),
		//		LEDs
			.LED_RD(LED_RD),
			.LED_WR(LED_WR),
			.LED_A(LED_A),
			.LED_B(LED_B),
			.LED_PLSR(LED_PLSR),
			.LED_L1(LED_L1),
			.LED_SPARE(LED_SPARE),
			.LED_ORBIT(LED_ORBIT),
			.LED_BC(LED_BC),
			.LED_PP(LED_PP),
			.LED_BUSY(LED_BUSY),
			.LED_L0(LED_L0),
		// Clock
			.DL_BC(clk_BC),
			.BC_DELAY(BC_DELAY),
			.LED_LOCK(LED_LOCK),
		// Test PINs
			.TEST_C1(TEST_C1),
			.TEST_C2(TEST_C2),
			.TEST_C3(TEST_C3),
			.TEST_C4(TEST_C4),
			.TEST_C5(TEST_C5),
			.TEST_C6(TEST_C6),
			.TEST_C7(TEST_C7),
			.TEST_C8(TEST_C8),
		// Logic Analyzer
			.LA_CLOCK(LA_CLOCK),
			.LA_C3_6(LA_C3_6),
			.LA_A2_0(LA_A2_0),
			.LA_A3_7(LA_A3_7),
			.LA_C3_7(LA_C3_7),
			.LA_A3_6(LA_A3_6),
			.LA_C3_5(LA_C3_5),
			.LA_A3_4(LA_A3_4),
			.LA_A3_3(LA_A3_3),
			.LA_C3_4(LA_C3_4),
			.LA_A3_2(LA_A3_2),
			.LA_A3_1(LA_A3_1),
			.LA_A2_6(LA_A2_6),
			.LA_A2_7(LA_A2_7),
			.LA_A3_0(LA_A3_0),
			.LA_A2_5(LA_A2_5),
			.LA_A2_4(LA_A2_4),
			.LA_A2_1(LA_A2_1),
			.LA_A2_2(LA_A2_2),
			.LA_A2_3(LA_A2_3),
			.LA_A3_5(LA_A3_5),
		// SNAP-SHOT MEMORY
			.SSH_CLK(SSH_CLK),
			.SSH_A(SSH_A),
			.SSH_CE(SSH_CE),
			.SSH_WRITE(SSH_WRITE),
			.SSH_DQ(SSH_DQ),
		// FPGA configuring
			.INIT_DONE(INIT_DONE),
		// ADC
			.ADC_IN(ADC_IN),
			.ADC_CS(ADC_CS),
			.ADC_CLK(ADC_CLK),
			.ADC_SDATA(ADC_SDATA),
		// VME J2
			.BP_L1(BP_L1),
			.BP_ORBIT(BP_ORBIT),
			.OBP_BC(OBP_BC),
			.BP_L1_DATA(BP_L1_DATA),
			.BP_L2_STROBE(BP_L2_STROBE),
			.BP_L0(BP_L0),
			.BP_PREPULSE(BP_PREPULSE),
			.BP_L2_DATA(BP_L2_DATA),
			.D(D),
		// VME FPGA
			.ADD(ADD),
			.SPARE_1(SPARE_1),
			.SPARE_2(SPARE_2),
			.SPARE_3(SPARE_3),
			.SPARE_4(SPARE_4),
			.WRITE(WRITE),
			.MRESET(MRESET),
			.DWB(DWB),
			.STROBE(STROBE),
			.MSTROBE(MSTROBE),
			.VME_CLK(VME_CLK));

	FEE_GTU_emu fee(
		.clk(clk_BC),
		.TTCtrd_A(OUT_L1),
		.reset(D[15]),
		.BUSY(IN_BUSY1));

	CTP_LTU_emu ctp(
		.clk(clk_BC),
        	.reset(D[15]),
        	.BUSY(OUT_BUSY),
        	.LM_SA(OUT_SPARE),
        	.LM_GL(LM_GL),
        	.TTC_A(TTC_A));
	
	reg [31:0] D_reg;
	
	always @(posedge OUT_L1)
	begin
		time_2 <= $time;
	end
	
	initial begin
		// Set variables for graphical waveoutput
		$dumpfile("LTU-T.vcd");
		$dumpvars(0,TestBench);

		// initialize all registers with 0
		TTC_B <= 0;
		CON_SPARE1 <= 0;
		CON_SPARE2 <= 0;
		CON_SPARE3 <= 0;
		CON_SPARE4 <= 0;
		IN_PULSER <= 0;
		IN_SPARE <= 0;
		IN_LVDS <= 0;
		IN_BUSY2 <= 0;
		//SSH_DQ <= 0;
		//ADC_SDATA <= 0;
		D_reg <= 0;
		ADD <= 0;
		MRESET <= 0;
		STROBE <= 0;
		MSTROBE <= 0;
		VME_CLK <= 0;
		
		// send Reset
		#200 D_reg <= reset_LTU;
		#15 MRESET <= 1;
		#10 D_reg <= 0;
		#15 MRESET <= 0;
		
		// #10;
		// @(posedge clk_BC);
		// // start testing the LM
		// for (i=0; i <=25; i=i+1) begin
		// 	repeat(i) #1;
		// 	LM_GL <= 1;
		// 	time_1 <= $time;
		// 	#25 LM_GL <= 0;
		// 	#50;
		// 	data <= 3'b100;
		// 	#25 data <= 3'b000;
		// 	repeat(50-i) #1;
		// 	#175;
		// 	$display("delay of LM because of LTU-T: %t ns", (time_2 - time_1)/1000.0);
		// end
		
		// #10;
		// LM_GL <= 1;
		// #25 LM_GL <= 0;
		//
		// #275 TTC_A <= 1;
		// #25 TTC_A <= 0;
		//
		// @(negedge BUSY_GTU);
		// #100 data <= 3'b010;
		// #30 data <= 3'b011;
		// #20 data <= 3'b010;
		// #200 data <= 3'b000;
		#300000;
/*		repeat (10)
		begin
			@(posedge clk_BC) #18;
			LM_GL <= 1;
			#25 LM_GL <= 0;

			#275 TTC_A <= 1;
			#25 TTC_A <= 0;
			
			#5275 TTC_A <= 1;
			#50 TTC_A <= 0;
			
			@(negedge IN_BUSY1) #100;
		end

			@(posedge clk_BC) #18;
			LM_GL <= 1;
			#25 LM_GL <= 0;

			#225 TTC_A <= 1;
			#25 TTC_A <= 0;
			
			#5275 TTC_A <= 1;
			#50 TTC_A <= 0;
			@(negedge IN_BUSY1) #100;
			
			@(posedge clk_BC) #18;
			LM_GL <= 1;
			#25 LM_GL <= 0;

			#310 TTC_A <= 1;
			#25 TTC_A <= 0;
			
			#5275 TTC_A <= 1;
			#50 TTC_A <= 0;
			#100;			
*/
		while (OUT_BUSY == 1) #1;
		#10;
		@(posedge clk_BC) D_reg <= enable_seq | mode_pulser;
		#60 IN_PULSER <= 1;
		#25 IN_PULSER <= 0;

		#1015 IN_PULSER <= 1;
		#25 IN_PULSER <= 0;
		#10000;

		while (OUT_BUSY == 1) #1;
		#10;
		@(posedge clk_BC) D_reg <= enable_seq | mode_BC;
		#60 IN_PULSER <= 1;
		#25 IN_PULSER <= 0;

		#1015 IN_PULSER <= 1;
		#25 IN_PULSER <= 0;
		#10000;

		while (OUT_BUSY == 1) #1;
		#10;
		@(posedge clk_BC) D_reg <= enable_seq | mode_rnd;
		#60 IN_PULSER <= 1;
		#25 IN_PULSER <= 0;

		#1015 IN_PULSER <= 1;
		#25 IN_PULSER <= 0;

		#10000 D_reg <= 0;		

	end

	assign D = D_reg;
endmodule