`timescale 1 ns/1 ns

module TestBench();

	wire clk_40;
	wire clk_160;

	FastClk fast(clk_160);
	BC_clk slow(clk_40);

	reg pc_reset;
	reg LM_GL;
	reg TTC_A;
	reg BUSY_GTU;
	reg pc_clear_counter;
	reg [4:0] pc_timer_width;
	reg [7:0] pc_timer_L0;
	reg [11:0] pc_timer_L1;
	reg [7:0] pc_L0_delay;
	reg [7:0] pc_L1_delay;
	reg [9:0] pc_MCM_reset_time_noL0;
	reg [9:0] pc_MCM_reset_time_noL1;

	wire LM;
	wire L0;
	wire L1;
	wire pc_timer_reset;
	wire [31:0] pc_LM_counter;
	wire [31:0] pc_L0_counter;
	wire [31:0] pc_L1_counter;
	wire [27:0] pc_LM_rate;
	wire [27:0] pc_L0_rate;
	wire [27:0] pc_L1_rate;
	wire pc_BUSY;
	wire [11:0] pc_mon_state_PC;

	reg CTP_enable;
	reg CTP_pulser;
	reg CTP_start_single;
	reg [1:0] CTP_mode;
	reg [7:0] CTPEmu_LMSA;
	reg [31:0] CTPEmu_freq;
	reg [31:0] CTPEmu_threshold;
	reg [7:0] CTP_MCM_reset_time_noL0;
	reg [7:0] CTP_MCM_reset_time_noL1;
	reg [10:0] CTP_time_L1;

	wire CTP_reset;
	wire CTP_LM;
	wire CTP_LM_SA;
	wire [31:0] CTP_rnd;
	wire [5:0] CTP_mon_state;

	Protocol_conv pc(
		.clk(clk_160),
		.clk_BC(clk_40),
		.reset(pc_reset||CTP_reset),
		.LM_GL((CTP_enable&&CTP_LM)||(!CTP_enable&&LM_GL)),
		.TTC_A(TTC_A),
		.BUSY_GTU(BUSY_GTU),
		.clear_counter(pc_clear_counter),
		.timer_width(pc_timer_width),
		.timer_L0(pc_timer_L0),
		.timer_L1(pc_timer_L1),
		.L0_delay(pc_L0_delay),
		.L1_delay(pc_L1_delay),
		.MCM_reset_time_noL0(pc_MCM_reset_time_noL0),
		.MCM_reset_time_noL1(pc_MCM_reset_time_noL1),
		.LM(LM),
		.L0(L0),
		.L1(L1),
		.timer_reset(pc_timer_reset),
		.LM_counter(pc_LM_counter),
		.L0_counter(pc_L0_counter),
		.L1_counter(pc_L1_counter),
		.LM_rate(pc_LM_rate),
		.L0_rate(pc_L0_rate),
		.L1_rate(pc_L1_rate),
		.BUSY(pc_BUSY),
		.mon_state(pc_mon_state_PC));

	CTPEmulator emu(
		.clk(clk_40),
		.enable(CTP_enable),
		.pulser(CTP_pulser),
		.start_single(CTP_start_single),
		.mode(CTP_mode),
		.BUSY_GTU(BUSY_GTU),
		.BUSY_int(pc_BUSY),
		.LM_TTC(LM),
		.L0_TTC(L0),
		.L1_TTC(L1),
		.PC_timer_reset(pc_timer_reset),
		.CTPEmu_LMSA(CTPEmu_LMSA),
		.CTPEmu_freq(CTPEmu_freq),
		.CTPEmu_threshold(CTPEmu_threshold),
		.MCM_reset_time_noL0(CTP_MCM_reset_time_noL0),
		.MCM_reset_time_noL1(CTP_MCM_reset_time_noL1),
		.time_L1(CTP_time_L1),
		.reset(CTP_reset),
		.LM(CTP_LM),
		.LM_SA(CTP_LM_SA),
		.rnd(CTP_rnd),
		.mon_state(CTP_mon_state));



	initial
	begin
		pc_reset	<= 1;
		LM_GL		<= 0;
		TTC_A		<= 0;
		BUSY_GTU	<= 0;
		pc_clear_counter	<= 0;
		pc_timer_width	<= 4'd8;
		pc_timer_L0	= 8'd184 + 8'd4 - 8'd3;
		pc_timer_L1	= 12'd1040 + 12'd4 - 12'd2;
		pc_L0_delay	<= 8'd0;
		pc_L1_delay	<= 8'd16;

		CTP_MCM_reset_time_noL0	= 8'd18;
		CTP_MCM_reset_time_noL1	= 8'd44;
		pc_MCM_reset_time_noL0 <= CTP_MCM_reset_time_noL0 << 2;
		pc_MCM_reset_time_noL1 <= CTP_MCM_reset_time_noL1 << 2;

		CTP_enable 	<= 0;
		CTP_pulser	<= 0;
		CTP_start_single	<= 0;
		CTP_mode	<= 2'd2;
		CTPEmu_LMSA	<= 8'h26;
		CTPEmu_freq	<= 32'h165;//9C15;
		CTPEmu_threshold	<= 32'hFF44C117;//FFFE5C0A;
		CTP_time_L1 	<= (pc_timer_L1 >> 2) + 1'b1;

		#25 pc_reset <= 0;

		#200 CTP_enable <= 1;
	end

	always @(posedge CTP_LM_SA)
	begin
		#150;
		if (CTP_rnd > 32'b0000_1000_0000_0000_0000_0000_0000_0000)
		begin
				TTC_A <= 1;
			#25 	TTC_A <= 0;
			#6475 	
			if (CTP_rnd > 32'b0100_0000_0000_0000_0000_0000_0000_0000)
			begin
					TTC_A <= 1;
				#50 	TTC_A <= 0;
			end
		end
	end

	always @(posedge L0)
	begin
		#6200 	BUSY_GTU <= 1;
		#800	BUSY_GTU <= 0;
	end
endmodule