/*
 * protocol_converter.v
 * author: S. Klewin
 */

module ProtocolConverter(
	input clk,
	input reset,
	input reset_counter,
	input LM_GL,
	input TTC_A,
	input BUSY_GTU,
	input [5:0] LMtoL0ll,
	input [5:0] LMtoL0ul,
	input [5:0] LMtoL0delay,
	input [6:0] LMtoL0rec,
	input [8:0] LMtoL1ll,
	input [8:0] LMtoL1ul,
	input [8:0] LMtoL1delay,
	input [8:0] LMtoL1rec,
	input [10:0] LMtoL1acc,
	output reg busy,
	output reg LM,
	output reg L0,
	output reg L1,
	output reg [31:0] counter_ErrorState,
	output reg [31:0] counter_L0_e_1,
	output reg [31:0] counter_L0_e_2,
	output reg [31:0] counter_L0_e_3,
	output reg [31:0] counter_L0_e_4,
	output reg [31:0] counter_L0_e_m,
	output reg [31:0] counter_L0_l_1,
	output reg [31:0] counter_L0_l_2,
	output reg [31:0] counter_L0_l_3,
	output reg [31:0] counter_L0_l_4,
	output reg [31:0] counter_L0_l_m,
	output reg [31:0] counter_L1_e_1,
	output reg [31:0] counter_L1_e_2,
	output reg [31:0] counter_L1_e_3,
	output reg [31:0] counter_L1_e_4,
	output reg [31:0] counter_L1_e_m,
	output reg [31:0] counter_L1_l_1,
	output reg [31:0] counter_L1_l_2,
	output reg [31:0] counter_L1_l_3,
	output reg [31:0] counter_L1_l_4,
	output reg [31:0] counter_L1_l_m,
	output reg [7:0] state_mon);

	reg [5:0] LMtoL0ll_local;
	reg [5:0] LMtoL0ul_local;
	reg [5:0] LMtoL0delay_local;
	reg [6:0] LMtoL0rec_local;
	reg [8:0] LMtoL1ll_local;
	reg [8:0] LMtoL1ul_local;
	reg [8:0] LMtoL1delay_local;
	reg [8:0] LMtoL1rec_local;
	reg [10:0] LMtoL1acc_local;

	reg [3:0] state;
	parameter 
		S_GS 		= 4'd0,
		S_LM_sent 	= 4'd1,
		S_ready_for_L0 	= 4'd2,
		S_L0_received 	= 4'd3,
		S_L0_missed 	= 4'd4,
		S_L0_sent 	= 4'd5,
		S_ready_for_L1 	= 4'd6,
		S_L1_received 	= 4'd7,
		S_L1_missed 	= 4'd8,
		S_L1_sent 	= 4'd9,
		S_ERROR 	= 4'd10;

	reg [10:0] counter;

	reg ErrorState_cnt;

	wire [31:0] counter_neg_ErrorState;

	counter_32bit_up ErrorState_counter(
		.clock(!clk),
		.cnt_en(ErrorState_cnt),
		.sclr(reset_counter),
		.q(counter_neg_ErrorState));
	

	initial
	begin
		busy 	<= 1'b1;
		LM	<= 1'b0;
		L0	<= 1'b0;
		L1	<= 1'b0;
		state	<= S_GS;
		counter	<= 0;
		LMtoL0ll_local		<= 0;
		LMtoL0ul_local		<= 0;
		LMtoL0delay_local	<= 0;
		LMtoL0rec_local		<= 0;
		LMtoL1ll_local		<= 0;
		LMtoL1ul_local		<= 0;
		LMtoL1delay_local	<= 0;
		LMtoL1rec_local		<= 0;
		LMtoL1acc_local		<= 0;
		ErrorState_cnt <= 1'b0;
	end

	always @(posedge clk)
	begin
		if (reset == 1'b1)
		begin
			state_mon[7:4] <= 4'd0;
		end
		else if (state == S_ERROR)
		begin
			state_mon[7:4] <= state_mon[3:0];
		end

		state_mon[3:0] <= state;
	end

	always @(negedge clk)
	begin
		LM <= 1'b0;
		L0 <= 1'b0;
		L1 <= 1'b0;

		ErrorState_cnt <= 1'b0;

		if (reset == 1'b1)
		begin
			state <= S_ERROR;
			counter <= LMtoL0delay_local;
			busy <= 1'b1;
		end
		else
		begin
			case (state)
				S_GS:
				begin
					if (state_mon[3:0] == S_ERROR) ErrorState_cnt <= 1'b1;
					busy <= 1'b0;
					LMtoL0ll_local	<= LMtoL0ll;
					LMtoL0ul_local	<= LMtoL0ul;
					LMtoL0delay_local <= LMtoL0delay;
					LMtoL0rec_local	<= LMtoL0rec;
					LMtoL1ll_local	<= LMtoL1ll;
					LMtoL1ul_local	<= LMtoL1ul;
					LMtoL1delay_local <= LMtoL1delay;
					LMtoL1rec_local	<= LMtoL1rec;
					LMtoL1acc_local	<= LMtoL1acc;
					counter <= 0;

					if (BUSY_GTU == 1'b0)
					begin
						if (LM_GL == 1'b1)
						begin
							counter <= 1'b1;
							busy <= 1'b1;
							LM <= 1'b1;
							state <= S_LM_sent;
						end
					end
				end

				S_LM_sent:
				begin
					if (counter >= LMtoL0ll_local) state <= S_ready_for_L0;
					counter <= counter + 1'b1;
				end

				S_ready_for_L0:
				begin
					if (counter >= LMtoL0ul_local) 
					begin
						state <= S_L0_missed;
					end
					else
					begin
						if (TTC_A == 1'b1)
						begin
							if (counter >= LMtoL0delay_local)
							begin
								L0 <= 1'b1;
								state <= S_L0_sent;
							end
							else
							begin
								state <= S_L0_received;
							end
						end
					end
						
					counter <= counter + 1'b1;
				end

				S_L0_received:
				begin
					if (counter >= LMtoL0delay_local)
					begin
						L0 <= 1'b1;
						state <= S_L0_sent;
					end
					counter <= counter + 1'b1;
				end

				S_L0_missed:
				begin
					if (counter >= LMtoL0rec_local) state <= S_GS;
					counter <= counter + 1'b1;
				end

				S_L0_sent:
				begin
					if (counter >=LMtoL1ll_local) state <= S_ready_for_L1;
					counter <= counter + 1'b1;
				end

				S_ready_for_L1:
				begin
					if (counter >= LMtoL1ul_local)
					begin
						state <= S_L1_missed;
					end
					else
					begin
						if (TTC_A == 1'b1)
						begin
							if (counter >= LMtoL1delay_local)
							begin
								L1 <= 1'b1;
								state <= S_L1_sent;
							end
							else
							begin
								state <= S_L1_received;
							end
						end
					end
					
					counter <= counter + 1'b1;
				end

				S_L1_received:
				begin
					if (counter >= LMtoL1delay_local)
					begin
						L1 <= 1'b1;
						state <= S_L1_sent;
					end

					counter <= counter + 1'b1;
				end

				S_L1_missed:
				begin
					if (counter >= LMtoL1rec_local) state <= S_GS;
					
					counter <= counter + 1'b1;
				end

				S_L1_sent:
				begin
					if (counter >= LMtoL1acc_local) state <= S_GS;

					counter <= counter + 1'b1;
				end

				S_ERROR:
				begin
					if (counter >= LMtoL1rec_local) state <= S_GS;
					counter <= counter + 1'b1;
				end

				default:
				begin
					busy <= 1'b1;
					counter <= LMtoL0delay_local;
					state <= S_ERROR;
				end
			endcase
		end
	end

	reg L0_e_1_cnt;
	reg L0_e_2_cnt;
	reg L0_e_3_cnt;
	reg L0_e_4_cnt;
	reg L0_e_m_cnt;
	reg L0_l_1_cnt;
	reg L0_l_2_cnt;
	reg L0_l_3_cnt;
	reg L0_l_4_cnt;
	reg L0_l_m_cnt;
	reg L1_e_1_cnt;
	reg L1_e_2_cnt;
	reg L1_e_3_cnt;
	reg L1_e_4_cnt;
	reg L1_e_m_cnt;
	reg L1_l_1_cnt;
	reg L1_l_2_cnt;
	reg L1_l_3_cnt;
	reg L1_l_4_cnt;
	reg L1_l_m_cnt;

	wire [31:0] counter_neg_L1_l_1;
	wire [31:0] counter_neg_L1_l_2;
	wire [31:0] counter_neg_L1_l_3;
	wire [31:0] counter_neg_L1_l_4;
	wire [31:0] counter_neg_L1_l_m;
	wire [31:0] counter_neg_L1_e_1;
	wire [31:0] counter_neg_L1_e_2;
	wire [31:0] counter_neg_L1_e_3;
	wire [31:0] counter_neg_L1_e_4;
	wire [31:0] counter_neg_L1_e_m;
	wire [31:0] counter_neg_L0_l_1;
	wire [31:0] counter_neg_L0_l_2;
	wire [31:0] counter_neg_L0_l_3;
	wire [31:0] counter_neg_L0_l_4;
	wire [31:0] counter_neg_L0_l_m;
	wire [31:0] counter_neg_L0_e_1;
	wire [31:0] counter_neg_L0_e_2;
	wire [31:0] counter_neg_L0_e_3;
	wire [31:0] counter_neg_L0_e_4;
	wire [31:0] counter_neg_L0_e_m;

	counter_32bit_up L1_l_1(
		.clock(!clk),
		.cnt_en(L1_l_1_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L1_l_1));

	counter_32bit_up L1_l_2(
		.clock(!clk),
		.cnt_en(L1_l_2_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L1_l_2));

	counter_32bit_up L1_l_3(
		.clock(!clk),
		.cnt_en(L1_l_3_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L1_l_3));

	counter_32bit_up L1_l_4(
		.clock(!clk),
		.cnt_en(L1_l_4_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L1_l_4));

	counter_32bit_up L1_l_m(
		.clock(!clk),
		.cnt_en(L1_l_m_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L1_l_m));


	counter_32bit_up L1_e_1(
		.clock(!clk),
		.cnt_en(L1_e_1_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L1_e_1));

	counter_32bit_up L1_e_2(
		.clock(!clk),
		.cnt_en(L1_e_2_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L1_e_2));

	counter_32bit_up L1_e_3(
		.clock(!clk),
		.cnt_en(L1_e_3_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L1_e_3));

	counter_32bit_up L1_e_4(
		.clock(!clk),
		.cnt_en(L1_e_4_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L1_e_4));

	counter_32bit_up L1_e_m(
		.clock(!clk),
		.cnt_en(L1_e_m_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L1_e_m));


	counter_32bit_up L0_l_1(
		.clock(!clk),
		.cnt_en(L0_l_1_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L0_l_1));

	counter_32bit_up L0_l_2(
		.clock(!clk),
		.cnt_en(L0_l_2_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L0_l_2));

	counter_32bit_up L0_l_3(
		.clock(!clk),
		.cnt_en(L0_l_3_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L0_l_3));

	counter_32bit_up L0_l_4(
		.clock(!clk),
		.cnt_en(L0_l_4_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L0_l_4));

	counter_32bit_up L0_l_m(
		.clock(!clk),
		.cnt_en(L0_l_m_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L0_l_m));


	counter_32bit_up L0_e_1(
		.clock(!clk),
		.cnt_en(L0_e_1_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L0_e_1));

	counter_32bit_up L0_e_2(
		.clock(!clk),
		.cnt_en(L0_e_2_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L0_e_2));

	counter_32bit_up L0_e_3(
		.clock(!clk),
		.cnt_en(L0_e_3_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L0_e_3));

	counter_32bit_up L0_e_4(
		.clock(!clk),
		.cnt_en(L0_e_4_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L0_e_4));

	counter_32bit_up L0_e_m(
		.clock(!clk),
		.cnt_en(L0_e_m_cnt),
		.sclr(reset_counter),
		.q(counter_neg_L0_e_m));

	reg TTC_A_save;	

	reg [5:0] LMtoL0ll_local_1;
	reg [5:0] LMtoL0ll_local_2;
	reg [5:0] LMtoL0ll_local_3;
	reg [5:0] LMtoL0ul_local_1;
	reg [5:0] LMtoL0ul_local_2;
	reg [5:0] LMtoL0ul_local_3;
	reg [8:0] LMtoL1ll_local_1;
	reg [8:0] LMtoL1ll_local_2;
	reg [8:0] LMtoL1ll_local_3;
	reg [8:0] LMtoL1ul_local_1;
	reg [8:0] LMtoL1ul_local_2;
	reg [8:0] LMtoL1ul_local_3;

	always @(negedge clk)
	begin
		L0_e_1_cnt <= 0;
		L0_e_2_cnt <= 0;
		L0_e_3_cnt <= 0;
		L0_e_4_cnt <= 0;
		L0_e_m_cnt <= 0;
		L0_l_1_cnt <= 0;
		L0_l_2_cnt <= 0;
		L0_l_3_cnt <= 0;
		L0_l_4_cnt <= 0;
		L0_l_m_cnt <= 0;
		L1_e_1_cnt <= 0;
		L1_e_2_cnt <= 0;
		L1_e_3_cnt <= 0;
		L1_e_4_cnt <= 0;
		L1_e_m_cnt <= 0;
		L1_l_1_cnt <= 0;
		L1_l_2_cnt <= 0;
		L1_l_3_cnt <= 0;
		L1_l_4_cnt <= 0;
		L1_l_m_cnt <= 0;
	
		TTC_A_save <= TTC_A;

		if (state == S_GS)
		begin
			LMtoL0ll_local_1 <= LMtoL0ll-5'd1;
			LMtoL0ll_local_2 <= LMtoL0ll-5'd2;
			LMtoL0ll_local_3 <= LMtoL0ll-5'd3;
			LMtoL0ul_local_1 <= LMtoL0ul+5'd1;
			LMtoL0ul_local_2 <= LMtoL0ul+5'd2;
			LMtoL0ul_local_3 <= LMtoL0ul+5'd3;

			LMtoL1ll_local_1 <= LMtoL1ll-8'd1;
			LMtoL1ll_local_2 <= LMtoL1ll-8'd2;
			LMtoL1ll_local_3 <= LMtoL1ll-8'd3;
			LMtoL1ul_local_1 <= LMtoL1ul+8'd1;
			LMtoL1ul_local_2 <= LMtoL1ul+8'd2;
			LMtoL1ul_local_3 <= LMtoL1ul+8'd3;
		end
		else if (TTC_A == 1'b1 && TTC_A_save == 1'b0)
		begin
			if (state >= S_LM_sent && state < S_L0_sent)
			begin
				if (counter < LMtoL0ll_local_3) 	L0_e_m_cnt <= 1'b1;

				if (counter == LMtoL0ll_local)		L0_e_1_cnt <= 1'b1;
				if (counter == LMtoL0ll_local_1) 	L0_e_2_cnt <= 1'b1;
				if (counter == LMtoL0ll_local_2) 	L0_e_3_cnt <= 1'b1;
				if (counter == LMtoL0ll_local_3) 	L0_e_4_cnt <= 1'b1;
				if (counter == LMtoL0ul_local) 		L0_l_1_cnt <= 1'b1;
				if (counter == LMtoL0ul_local_1) 	L0_l_2_cnt <= 1'b1;
				if (counter == LMtoL0ul_local_2) 	L0_l_3_cnt <= 1'b1;
				if (counter == LMtoL0ul_local_3) 	L0_l_4_cnt <= 1'b1;

				if (counter > LMtoL0ul_local_3) 	L0_l_m_cnt <= 1'b1;

			end
			else if (state >= S_L0_sent && state < S_L1_sent)
			begin
				if (counter < LMtoL1ll_local_3) 	L1_e_m_cnt <= 1'b1;

				if (counter == LMtoL1ll_local)		L1_e_1_cnt <= 1'b1;
				if (counter == LMtoL1ll_local_1) 	L1_e_2_cnt <= 1'b1;
				if (counter == LMtoL1ll_local_2) 	L1_e_3_cnt <= 1'b1;
				if (counter == LMtoL1ll_local_3) 	L1_e_4_cnt <= 1'b1;
				if (counter == LMtoL1ul_local)		L1_l_1_cnt <= 1'b1;
				if (counter == LMtoL1ul_local_1)	L1_l_2_cnt <= 1'b1;
				if (counter == LMtoL1ul_local_2) 	L1_l_3_cnt <= 1'b1;
				if (counter == LMtoL1ul_local_3) 	L1_l_4_cnt <= 1'b1;

				if (counter > LMtoL1ul_local_3) 	L1_l_m_cnt <= 1'b1;
			end
		end
	end

	always @(posedge clk)
	begin
		counter_ErrorState <= counter_neg_ErrorState;
		counter_L1_l_1 <= counter_neg_L1_l_1;
		counter_L1_l_2 <= counter_neg_L1_l_2;
		counter_L1_l_3 <= counter_neg_L1_l_3;
		counter_L1_l_4 <= counter_neg_L1_l_4;
		counter_L1_l_m <= counter_neg_L1_l_m;
		counter_L1_e_1 <= counter_neg_L1_e_1;
		counter_L1_e_2 <= counter_neg_L1_e_2;
		counter_L1_e_3 <= counter_neg_L1_e_3;
		counter_L1_e_4 <= counter_neg_L1_e_4;
		counter_L1_e_m <= counter_neg_L1_e_m;
		counter_L0_l_1 <= counter_neg_L0_l_1;
		counter_L0_l_2 <= counter_neg_L0_l_2;
		counter_L0_l_3 <= counter_neg_L0_l_3;
		counter_L0_l_4 <= counter_neg_L0_l_4;
		counter_L0_l_m <= counter_neg_L0_l_m;
		counter_L0_e_1 <= counter_neg_L0_e_1;
		counter_L0_e_2 <= counter_neg_L0_e_2;
		counter_L0_e_3 <= counter_neg_L0_e_3;
		counter_L0_e_4 <= counter_neg_L0_e_4;
		counter_L0_e_m <= counter_neg_L0_e_m;
	end
endmodule