/*
 * communicator.v
 * Author: S. Klewin
 */

module Com(
	input clk,
	input reset,
	input [31:0] counter_Clock,
	input [31:0] counter_LM,
	input [31:0] counter_L0,
	input [31:0] counter_L1,
	input [31:0] counter_TTC_A,
	input [31:0] counter_LM_GL,
	input [31:0] counter_BUSY,
	input [31:0] counter_ErrorState,
	input [31:0] counter_L0_e_1,
	input [31:0] counter_L0_e_2,
	input [31:0] counter_L0_e_3,
	input [31:0] counter_L0_e_4,
	input [31:0] counter_L0_e_m,
	input [31:0] counter_L0_l_1,
	input [31:0] counter_L0_l_2,
	input [31:0] counter_L0_l_3,
	input [31:0] counter_L0_l_4,
	input [31:0] counter_L0_l_m,
	input [31:0] counter_L1_e_1,
	input [31:0] counter_L1_e_2,
	input [31:0] counter_L1_e_3,
	input [31:0] counter_L1_e_4,
	input [31:0] counter_L1_e_m,
	input [31:0] counter_L1_l_1,
	input [31:0] counter_L1_l_2,
	input [31:0] counter_L1_l_3,
	input [31:0] counter_L1_l_4,
	input [31:0] counter_L1_l_m,
	input [11:0] BCID,
	input [23:0] OrbitID,
	input [31:0] rnd,
	input ptcom_busy,
	input SSM_busy,
	input BUSY_GTU,
	input [17:0] SSM_data,
	input [9:0] ADDRESS,
	input STROBE,
	input WRITE,
	input [3:0] PC_ErrorState,
	output reg reset_counter,
	output reg LEDs_test,
	output reg [4:0] BC_delay,
	output reg L0L1_dis,
	output reg BUSY_dis,
	output reg LM_dis,
	output reg LM_GL_inv,
	output reg A_dis,
	output reg [1:0] B_dis,
	output reg [3:0] switchA,
	output reg [3:0] switchB,
	output reg [2:0] SSM_mode,
	output reg SSM_read,
	output reg SSM_start,
	output reg SSM_stop,
	output reg SSM_loop,
	output reg ptcom_en,
	output reg [2:0] ptcom_code,
	output reg ptcom_mux,
	output reg CTPEmu_enable,
	output reg [1:0] CTPEmu_mode,
	output reg CTPEmu_start,
	output reg [25:0] CTPEmu_freq,
	output reg [31:0] CTPEmu_threshold,
	output reg [31:0] CTPEmu_LMSA_threshold,
	output reg [5:0] LMtoLMSA,
	output reg [5:0] LMtoL0ll,
	output reg [5:0] LMtoL0ul,
	output reg [5:0] LMtoL0delay,
	output reg [6:0] LMtoL0rec,
	output reg [8:0] LMtoL1ll,
	output reg [8:0] LMtoL1ul,
	output reg [8:0] LMtoL1delay,
	output reg [8:0] LMtoL1rec,
	output reg [10:0] LMtoL1acc,
	inout [31:0] Data);

	reg [31:0] Data_out;
	reg [31:0] Data_in;
	reg [9:0] address;
	reg strobe;
	reg write;
	reg write_en;
	assign Data = write_en ? Data_out : 32'bz;

	reg [31:0] counter_Clock_copy;
	reg [31:0] counter_LM_copy;
	reg [31:0] counter_L0_copy;
	reg [31:0] counter_L1_copy;
	reg [31:0] counter_TTC_A_copy;
	reg [31:0] counter_LM_GL_copy;
	reg [31:0] counter_BUSY_copy;
	reg [31:0] counter_ErrorState_copy;
	reg [31:0] counter_L0_e_1_copy;
	reg [31:0] counter_L0_e_2_copy;
	reg [31:0] counter_L0_e_3_copy;
	reg [31:0] counter_L0_e_4_copy;
	reg [31:0] counter_L0_e_m_copy;
	reg [31:0] counter_L0_l_1_copy;
	reg [31:0] counter_L0_l_2_copy;
	reg [31:0] counter_L0_l_3_copy;
	reg [31:0] counter_L0_l_4_copy;
	reg [31:0] counter_L0_l_m_copy;
	reg [31:0] counter_L1_e_1_copy;
	reg [31:0] counter_L1_e_2_copy;
	reg [31:0] counter_L1_e_3_copy;
	reg [31:0] counter_L1_e_4_copy;
	reg [31:0] counter_L1_e_m_copy;
	reg [31:0] counter_L1_l_1_copy;
	reg [31:0] counter_L1_l_2_copy;
	reg [31:0] counter_L1_l_3_copy;
	reg [31:0] counter_L1_l_4_copy;
	reg [31:0] counter_L1_l_m_copy;
	reg [31:0] diff_channel_A;

	reg [31:0] rnd_read;

	`include "./addresses.v"

	`include "./build_stamp.v"

	parameter VERSION = 6'b01_0100;
	
//************************************************
//	Initialization of all registers
//************************************************
	initial begin
		// Output registers
		reset_counter	<= 1;
		LEDs_test	<= 0;
		L0L1_dis	<= 0;
		BUSY_dis	<= 0;
		LM_dis		<= 0;
		LM_GL_inv	<= 0;
		LMtoLMSA	<= 6'd42;	// 41 + 1 (offset)
		LMtoL0ll	<= 6'd47;
		LMtoL0ul	<= 6'd49;
		LMtoL0delay	<= 6'd48;
		LMtoL0rec	<= 7'd64;
		LMtoL1ll	<= 9'd307;
		LMtoL1ul	<= 9'd309;
		LMtoL1delay	<= 9'd312;
		LMtoL1rec	<= 9'd350;
		LMtoL1acc	<= 11'd1000;
		CTPEmu_enable 	<= 0;
		CTPEmu_mode 	<= 2'b10;
		CTPEmu_start	<= 0;
		CTPEmu_freq 	<= 26'b00_0000_0000_1001_1100_0100_0000;	// 1 kHz
		CTPEmu_threshold<= 32'b1000_0000_1111_0111_1011_0100_0110_0010;	// ~1 kHz
		CTPEmu_LMSA_threshold <= 0;
		switchA 	<= 4'b0000;
		switchB 	<= 4'b0000;
		ptcom_en	<= 0;
		ptcom_code	<= 0;
		ptcom_mux	<= 0;
		A_dis		<= 1'b1;//0
		B_dis		<= 2'b00;
		SSM_mode	<= 0;
		SSM_read	<= 0;
		SSM_start	<= 0;
		SSM_stop	<= 0;
		SSM_loop	<= 0;
		BC_delay 	<= 5'b0_0000;

		// Internalt registers
		address		<= 0;
		strobe		<= 0;
		write		<= 0;
		write_en	<= 0;
		Data_out	<= 0;
		Data_in		<= 0;

		// Counter copies
		counter_Clock_copy <= 0;
		counter_LM_copy <= 0;
		counter_L0_copy <= 0;
		counter_L1_copy <= 0;
		counter_TTC_A_copy <= 0;
		counter_LM_GL_copy <= 0;
		counter_BUSY_copy <= 0;
		counter_ErrorState_copy <= 0;
		counter_L0_e_1_copy <= 0;
		counter_L0_e_2_copy <= 0;
		counter_L0_e_3_copy <= 0;
		counter_L0_e_4_copy <= 0;
		counter_L0_e_m_copy <= 0;
		counter_L0_l_1_copy <= 0;
		counter_L0_l_2_copy <= 0;
		counter_L0_l_3_copy <= 0;
		counter_L0_l_4_copy <= 0;
		counter_L0_l_m_copy <= 0;
		counter_L1_e_1_copy <= 0;
		counter_L1_e_2_copy <= 0;
		counter_L1_e_3_copy <= 0;
		counter_L1_e_4_copy <= 0;
		counter_L1_e_m_copy <= 0;
		counter_L1_l_1_copy <= 0;
		counter_L1_l_2_copy <= 0;
		counter_L1_l_3_copy <= 0;
		counter_L1_l_4_copy <= 0;
		counter_L1_l_m_copy <= 0;
	end
	
	always @(posedge clk)
 	begin
		address <= ADDRESS;
		strobe <= STROBE;
		write <= WRITE;
		Data_in <= Data;
		reset_counter <= 0;
		write_en <= 1'b0;
		Data_out <= 32'b0;
		ptcom_en <= 0;
		SSM_start <= 0;
		SSM_stop <= 0;
		CTPEmu_start <= 0;

		diff_channel_A <= counter_TTC_A - counter_L1 - counter_L0;
		rnd_read <= rnd;

		if (reset == 1'b1)
		begin
			reset_counter	<= 1;
			LEDs_test	<= 0;
			L0L1_dis	<= 0;
			BUSY_dis	<= 0;
			LM_dis		<= 0;
			LM_GL_inv	<= 0;
			LMtoLMSA	<= 6'd42;	// 41 + 1(offset)
			LMtoL0ll	<= 6'd47;
			LMtoL0ul	<= 6'd49;
			LMtoL0delay	<= 6'd48;
			LMtoL0rec	<= 7'd64;
			LMtoL1ll	<= 9'd307;
			LMtoL1ul	<= 9'd309;
			LMtoL1delay	<= 9'd312;
			LMtoL1rec	<= 9'd350;
			LMtoL1acc	<= 11'd1000;
			CTPEmu_enable 	<= 0;
			CTPEmu_mode 	<= 2'b10;
			CTPEmu_start	<= 0;
			CTPEmu_freq 	<= 26'b00_0000_0000_1001_1100_0100_0000;	// 1 kHz	
			CTPEmu_threshold<= 32'b1000_0000_1111_0111_1011_0100_0110_0010; // ~1 kHz	
			CTPEmu_LMSA_threshold <= 0;
			switchA 	<= 4'b0000;
			switchB 	<= 4'b0000;
			ptcom_en	<= 0;
			ptcom_code	<= 0;
			ptcom_mux	<= 0;
			A_dis		<= 1'b1;//0
			B_dis		<= 2'b00;
			SSM_mode	<= 0;
			SSM_read	<= 0;
			SSM_start	<= 0;
			SSM_stop 	<= 0;
			SSM_loop	<= 0;
			BC_delay 	<= 5'b0_0000;
		end
		else
		begin
			if (strobe)
			begin
				case(address)
//************************************************
//	Version / basic config
//************************************************
					SVN_REV:
					begin
						if (!write)
						begin
							Data_out[31:0] <= revision;
							write_en <= 1;
						end
					end
	
					BUILD_DATE:
					begin
						if (!write)
						begin
							Data_out[31:0] <= b_date;
							write_en <= 1;
						end
					end
		
					BUILD_TIME:
					begin
						if (!write)
						begin
							Data_out[31:0] <= {b_clean,b_time};
							write_en <= 1;
						end
					end
					
					L_VERSION_ADD:
					begin
						if (!write)
						begin
							Data_out[5:0] <= VERSION;
							write_en <= 1;
						end
					end

					BC_DELAY:
					begin
						if (write) BC_delay <= Data_in[4:0];
						else
						begin
							Data_out[4:0] <= BC_delay;
							write_en <= 1;
						end
					end

					TEST_ADD:
					begin
						if (write) LEDs_test <= Data_in[0];
						else		
						begin
							Data_out[0] <= LEDs_test;
							write_en <= 1;
						end
					end

					ERROR_STATE:
					begin
						if (!write)
						begin
							Data_out[3:0] <= PC_ErrorState;
							write_en <= 1;
						end
					end

//************************************************
//	Counter
//************************************************
					COUNTER_RESET:
					begin
						if (write) reset_counter <= 1;
					end

					COUNTER_LOCK:
					begin
						if (write)
						begin
							counter_Clock_copy <= counter_Clock;
							counter_LM_copy <= counter_LM;
							counter_L0_copy <= counter_L0;
							counter_L1_copy <= counter_L1;
							counter_TTC_A_copy <= counter_TTC_A;
							counter_LM_GL_copy <= counter_LM_GL;
							counter_BUSY_copy <= counter_BUSY;
							counter_ErrorState_copy <= counter_ErrorState;
							counter_L0_e_1_copy <= counter_L0_e_1;
							counter_L0_e_2_copy <= counter_L0_e_2;
							counter_L0_e_3_copy <= counter_L0_e_3;
							counter_L0_e_4_copy <= counter_L0_e_4;
							counter_L0_e_m_copy <= counter_L0_e_m;
							counter_L0_l_1_copy <= counter_L0_l_1;
							counter_L0_l_2_copy <= counter_L0_l_2;
							counter_L0_l_3_copy <= counter_L0_l_3;
							counter_L0_l_4_copy <= counter_L0_l_4;
							counter_L0_l_m_copy <= counter_L0_l_m;
							counter_L1_e_1_copy <= counter_L1_e_1;
							counter_L1_e_2_copy <= counter_L1_e_2;
							counter_L1_e_3_copy <= counter_L1_e_3;
							counter_L1_e_4_copy <= counter_L1_e_4;
							counter_L1_e_m_copy <= counter_L1_e_m;
							counter_L1_l_1_copy <= counter_L1_l_1;
							counter_L1_l_2_copy <= counter_L1_l_2;
							counter_L1_l_3_copy <= counter_L1_l_3;
							counter_L1_l_4_copy <= counter_L1_l_4;
							counter_L1_l_m_copy <= counter_L1_l_m;
						end
					end

					COUNTER_CLOCK:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_Clock_copy;
							write_en <= 1;
						end
					end

					COUNTER_LM:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_LM_copy;
							write_en <= 1;
						end
					end

					COUNTER_L0:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L0_copy;
							write_en <= 1;
						end
					end

					COUNTER_L1:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L1_copy;
							write_en <= 1;
						end
					end

					COUNTER_TTCA:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_TTC_A_copy;
							write_en <= 1;
						end
					end

					COUNTER_LMGL:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_LM_GL_copy;
							write_en <= 1;
						end
					end

					COUNTER_BUSY:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_BUSY_copy;
							write_en <= 1;
						end
					end

					COUNTER_ERROR:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_ErrorState_copy;
							write_en <= 1;
						end
					end

					DIFF_CHANNEL_A:
					begin
						if (!write)
						begin
							diff_channel_A <= diff_channel_A;
							Data_out[31:0] <= diff_channel_A;
							write_en <= 1;
						end
					end

					COUNTER_L0_E_1:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L0_e_1_copy;
							write_en <= 1;
						end
					end

					COUNTER_L0_E_2:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L0_e_2_copy;
							write_en <= 1;
						end
					end

					COUNTER_L0_E_3:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L0_e_3_copy;
							write_en <= 1;
						end
					end

					COUNTER_L0_E_4:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L0_e_4_copy;
							write_en <= 1;
						end
					end

					COUNTER_L0_E_M:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L0_e_m_copy;
							write_en <= 1;
						end
					end

					COUNTER_L0_L_1:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L0_l_1_copy;
							write_en <= 1;
						end
					end

					COUNTER_L0_L_2:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L0_l_2_copy;
							write_en <= 1;
						end
					end

					COUNTER_L0_L_3:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L0_l_3_copy;
							write_en <= 1;
						end
					end

					COUNTER_L0_L_4:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L0_l_4_copy;
							write_en <= 1;
						end
					end

					COUNTER_L0_L_M:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L0_l_m_copy;
							write_en <= 1;
						end
					end

					COUNTER_L1_E_1:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L1_e_1_copy;
							write_en <= 1;
						end
					end

					COUNTER_L1_E_2:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L1_e_2_copy;
							write_en <= 1;
						end
					end

					COUNTER_L1_E_3:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L1_e_3_copy;
							write_en <= 1;
						end
					end

					COUNTER_L1_E_4:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L1_e_4_copy;
							write_en <= 1;
						end
					end

					COUNTER_L1_E_M:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L1_e_m_copy;
							write_en <= 1;
						end
					end

					COUNTER_L1_L_1:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L1_l_1_copy;
							write_en <= 1;
						end
					end

					COUNTER_L1_L_2:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L1_l_2_copy;
							write_en <= 1;
						end
					end

					COUNTER_L1_L_3:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L1_l_3_copy;
							write_en <= 1;
						end
					end

					COUNTER_L1_L_4:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L1_l_4_copy;
							write_en <= 1;
						end
					end

					COUNTER_L1_L_M:
					begin
						if (!write)
						begin
							Data_out[31:0] <= counter_L1_l_m_copy;
							write_en <= 1;
						end
					end
//************************************************
//	TTC-B info
//************************************************
					BC_ID:
					begin
						if (!write);
						begin
							Data_out[11:0] <= BCID;
							write_en <= 1;
						end
					end

					ORBIT_ID:
					begin
						if (!write);
						begin
							Data_out[23:0] <= OrbitID;
							write_en <= 1;
						end
					end

//************************************************
//	Inputs
//************************************************
					BUSY_DISABLE:
					begin
						if (write) BUSY_dis <= Data_in[0];
						else
						begin
							Data_out[0] <= BUSY_dis;
							Data_out[1] <= BUSY_GTU;
							write_en <= 1;
						end
					end

					A_DISABLE:
					begin
						if (write) A_dis <= Data_in[0];
						else
						begin
							Data_out[0] <= A_dis;
							write_en <= 1;
						end
					end

					B_DISABLE:
					begin
						if (write) B_dis <= Data_in[1:0];
						else
						begin
							Data_out[1:0] <= B_dis;
							write_en <= 1;
						end
					end

					L0L1_DISABLE:
					begin
						if (write) L0L1_dis <= Data_in[0];
						else
						begin
							Data_out[0] <= L0L1_dis;
							write_en <= 1;
						end
					end

					LMGL_INVERT:
					begin
						if (write) LM_GL_inv <= Data_in[0];
						else
						begin
							Data_out[0] <= LM_GL_inv;
							write_en <= 1;
						end
					end

					LMGL_DISABLE:
					begin
						if (write) LM_dis <= Data_in[0];
						else
						begin
							Data_out[0] <= LM_dis;
							write_en <= 1;
						end
					end
		
					SWITCH_A:
					begin
						if (write) switchA <= Data_in[3:0];
						else
						begin
							Data_out[3:0] <= switchA;
							write_en <= 1;
						end
					end
					
					SWITCH_B:
					begin
						if (write) switchB <= Data_in[3:0];
						else
						begin
							Data_out[3:0] <= switchB;
							write_en <= 1;
						end
					end

//************************************************
//	SSM
//************************************************
					SSM_START:
					begin
						SSM_start <= 1;

						if (write) 
						begin
							if (!SSM_busy)
							begin
								SSM_read <= 0;
							end
						end
						else
						begin
							SSM_read <= 1;
							Data_out[17:0] <= SSM_data;
							write_en <= 1;
						end
					end

					SSM_MODE:
					begin
						if (write) SSM_mode <= Data_in[2:0];
						else
						begin
							Data_out[4:0] <= {SSM_busy,SSM_read,SSM_mode};
							write_en <= 1;
						end
					end

					SSM_LOOP:
					begin
						if (write) SSM_loop <= Data_in[0];
						else
						begin
							Data_out[0] <= SSM_loop;
							write_en <= 1;
						end
					end

					SSM_STOP:
					begin
						if (write)
						begin
							SSM_stop <= 1'b1;
						end
					end

//************************************************
//	Pretrigger commands
//************************************************
					PTCOM_EN:
					begin
						if (write) ptcom_mux <= Data_in[0];
						else
						begin
							Data_out[0] <= ptcom_mux;
							write_en <= 1;
						end
					end

					PTCOM_CODE:
					begin
						if (write)
						begin
							if (ptcom_mux)
							begin
								if (!ptcom_busy)
								begin
									ptcom_code <= Data_in[2:0];
									ptcom_en <= 1;
								end
							end
							else 
							begin
								ptcom_code <= 0;
							end
						end
						else
						begin
							Data_out[2:0] <= ptcom_code;
							write_en <= 1;
						end
					end


//************************************************
//	CTP Emulator
//************************************************
					CTPEMU_START:
					begin
						if (write) CTPEmu_start <= 1;
					end

					CTPEMU_FREQ:
					begin
						if (write) CTPEmu_freq <= Data_in[25:0];
						else
						begin
							Data_out[25:0] <= CTPEmu_freq;
							write_en <= 1;
						end
					end

					CTPEMU_THR:
					begin
						if (write) CTPEmu_threshold <= Data_in[31:0];
						else
						begin
							Data_out[31:0] <= CTPEmu_threshold;
							write_en <= 1;
						end
					end

					CTPEMU_LMSA_THR:
					begin
						if (write) CTPEmu_LMSA_threshold <= Data_in[31:0];
						else
						begin
							Data_out[31:0] <= CTPEmu_LMSA_threshold;
							write_en <= 1;
						end
					end

					CTPEMU_ENABLE:
					begin
						if (write) CTPEmu_enable <= Data_in[0];
						else
						begin
							Data_out[0] <= CTPEmu_enable;
							write_en <= 1;
						end
					end

					CTPEMU_MODE:
					begin
						if (write) CTPEmu_mode <= Data_in[1:0];
						else
						begin
							Data_out[1:0] <= CTPEmu_mode;
							write_en <= 1;
						end
					end
	
					RND:
					begin
						if (!write)
						begin
							rnd_read <= rnd_read;
							Data_out <= rnd_read;
							write_en <= 1;
						end
					end

//************************************************
//	Timings
//************************************************
					LMTOLMSA:
					begin
						if (write) LMtoLMSA <= Data_in[5:0];
						else
						begin
							Data_out [5:0] <= LMtoLMSA;
							write_en <= 1;
						end
					end

					LMTOL0_LL:
					begin
						if (write) LMtoL0ll <= Data_in[5:0];
						else
						begin
							Data_out [5:0] <= LMtoL0ll;
							write_en <= 1;
						end
					end

					LMTOL0_UL:
					begin
						if (write) LMtoL0ul <= Data_in[5:0];
						else
						begin
							Data_out [5:0] <= LMtoL0ul;
							write_en <= 1;
						end
					end

					LMTOL0_DELAY:
					begin
						if (write) LMtoL0delay <= Data_in[5:0];
						else
						begin
							Data_out [5:0] <= LMtoL0delay;
							write_en <= 1;
						end
					end

					LMTOL0_REC:
					begin
						if (write) LMtoL0rec <= Data_in[6:0];
						else
						begin
							Data_out [6:0] <= LMtoL0rec;
							write_en <= 1;
						end
					end

					LMTOL1_LL:
					begin
						if (write) LMtoL1ll <= Data_in[8:0];
						else
						begin
							Data_out [8:0] <= LMtoL1ll;
							write_en <= 1;
						end
					end

					LMTOL1_UL:
					begin
						if (write) LMtoL1ul <= Data_in[8:0];
						else
						begin
							Data_out [8:0] <= LMtoL1ul;
							write_en <= 1;
						end
					end

					LMTOL1_DELAY:
					begin
						if (write) LMtoL1delay <= Data_in[8:0];
						else
						begin
							Data_out [8:0] <= LMtoL1delay;
							write_en <= 1;
						end
					end

					LMTOL1_REC:
					begin
						if (write) LMtoL1rec <= Data_in[8:0];
						else
						begin
							Data_out [8:0] <= LMtoL1rec;
							write_en <= 1;
						end
					end

					LMTOL1_ACC:
					begin
						if (write) LMtoL1acc <= Data_in[10:0];
						else
						begin
							Data_out [10:0] <= LMtoL1acc;
							write_en <= 1;
						end
					end

				endcase
			end
		end
	end
	
endmodule