module SSMcontroler(
	input clk,
	input clk_180,
	input reset,
	input SSM_start,
	input SSM_stop,
	input SSM_loop,
	input SSM_read,
	input [2:0] SSM_mode,
	input [31:0] counter_Clock,
        input [7:0] PC_state_mon,
        input [8:0] CTPEmu_state_mon,
     	input [31:0] rnd,
   	input inp_LM,
        input inp_TTC_A,
        input inp_TTC_B,
        input inp_PLSR,
        input inp_BUSY,
        input outp_L1,
        input outp_SPARE,
        input outp_ORBIT,
        input outp_BUSY,
	input CTPEmu_LM,
	input LM_GL_sync,
	input TTC_A_sync,
	input TTCtrd_A,
	input [11:0] BCID,
	input [23:0] OrbitID,
        output SSM_CE,
	output SSM_CLK,
        output reg SSM_WRITE,
	output reg [19:0] SSM_A,
	output reg [17:0] SSM_data,
	output reg SSM_busy,
	inout [17:0] SSM_DQ);

	reg [17:0] Data_out;
        assign SSM_CE = 1'b0;
	assign SSM_DQ = SSM_WRITE ? 18'bz : Data_out;
	
	reg [1:0] state_read;
	reg [1:0] state_write;

	initial
	begin
		SSM_WRITE	<= 1'b1;
		SSM_busy	<= 0;
		SSM_A		<= 0;
		Data_out	<= 0;
		state_read	<= 0;
		state_write	<= 0;
	end

	assign SSM_CLK = clk_180;

	always @(posedge clk)
	begin
		if (reset)
		begin
			SSM_WRITE	<= 1'b1;
			SSM_busy	<= 0;
			SSM_A		<= 0;
			Data_out	<= 0;
			state_read	<= 0;
			state_write	<= 0;
		end
		else
		begin
			Data_out <= 0;
			// READING
			//
			if (SSM_read == 1'b1)
			begin  
				SSM_WRITE <= 1'b1;
				case (state_read)
					2'b00:
					begin
						if (SSM_start == 1'b1)
						begin
							SSM_busy <= 1'b1;
							state_read <= state_read + 1'b1;
						end
					end
					
					2'b01:
					begin
						if (SSM_start == 1'b0)
						begin
							state_read <= state_read + 1'b1;
						end
					end
		
					2'b10:
					begin
						SSM_data <= SSM_DQ;
						state_read <= state_read + 1'b1;
					end
	
					2'b11:
					begin
						SSM_busy <= 0;
						state_read <= state_read + 1'b1;
	
						SSM_A <= SSM_A + 1'b1;
					end
				endcase
			end
			else
			// WRITING
			//
			begin
				SSM_WRITE <= 1'b0;
	
				case (state_write)
					2'b00:
					begin
						if (SSM_start == 1'b1)
						begin
							SSM_busy <= 1'b1;
							state_write <= state_write + 1'b1;
							SSM_A <= 0;
						end
					end
				
					2'b01:
					begin
						if (SSM_start == 1'b0)
						begin
							state_write <= state_write + 1'b1;
						end
					end
	
					2'b10:
					begin
						case (SSM_mode)
							3'd0:
							begin  
								Data_out <= {1'b0,CTPEmu_state_mon, PC_state_mon};
							end
											
							3'd1:
							begin 
								Data_out <= {1'b0,CTPEmu_LM,LM_GL_sync,TTC_A_sync,TTCtrd_A,PC_state_mon[3:0],inp_BUSY,outp_BUSY,inp_TTC_B,outp_ORBIT,inp_LM, inp_TTC_A, outp_SPARE,outp_L1,inp_PLSR};
							end
		
							3'd2:
							begin
								Data_out <= rnd[17:0];
							end
	
							3'd3:
							begin
								Data_out <= counter_Clock[17:0];
							end
		
							3'd4:
							begin
								Data_out <= SSM_A[17:0];
							end
	
							3'd5:
							begin
								Data_out <= {6'b00_0000,BCID};
							end

							3'd6:
							begin
								Data_out <= 18'b10_1010_1010_1010_1010;
							end
						endcase
					
						SSM_A <= SSM_A + 1'b1;
				
						if (SSM_loop == 1'b1)
						begin
							if (SSM_stop == 1'b1) 
							begin
								state_write <= state_write + 1'b1;
							end
						end
						else
						begin
							if (SSM_A == 20'b1111_1111_1111_1111_1111)
							begin 
								state_write <= state_write + 1'b1; 
							end
						end
					end
	
					2'b11:
					begin
						SSM_busy <= 0;
						state_write <= state_write + 1'b1;
					end
				endcase
			end
		end
	end
endmodule