// megafunction wizard: %RAM: 2-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: RAM_2port_1024x32.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version // ************************************************************ //Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. //altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" DEVICE_FAMILY="Cyclone" INDATA_ACLR_A="NONE" INIT_FILE="./MersenneTwister/MT_RAM_init.mif" NUMWORDS_A=1024 NUMWORDS_B=1024 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="M4K" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 WIDTHAD_B=10 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a //VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:04:00:SJ cbx_cycloneii 2013:06:12:18:04:00:SJ cbx_lpm_add_sub 2013:06:12:18:04:00:SJ cbx_lpm_compare 2013:06:12:18:04:00:SJ cbx_lpm_decode 2013:06:12:18:04:00:SJ cbx_lpm_mux 2013:06:12:18:04:00:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:04:00:SJ cbx_stratixii 2013:06:12:18:04:00:SJ cbx_stratixiii 2013:06:12:18:04:00:SJ cbx_stratixv 2013:06:12:18:04:00:SJ cbx_util_mgl 2013:06:12:18:04:00:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 //synthesis_resources = M4K 8 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on (* ALTERA_ATTRIBUTE = {"OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *) module RAM_2port_1024x32_altsyncram ( address_a, address_b, clock0, data_a, q_b, wren_a) /* synthesis synthesis_clearbox=1 */; input [9:0] address_a; input [9:0] address_b; input clock0; input [31:0] data_a; output [31:0] q_b; input wren_a; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 [9:0] address_b; tri1 clock0; tri1 [31:0] data_a; tri0 wren_a; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire [0:0] wire_ram_block1a_0portbdataout; wire [0:0] wire_ram_block1a_1portbdataout; wire [0:0] wire_ram_block1a_2portbdataout; wire [0:0] wire_ram_block1a_3portbdataout; wire [0:0] wire_ram_block1a_4portbdataout; wire [0:0] wire_ram_block1a_5portbdataout; wire [0:0] wire_ram_block1a_6portbdataout; wire [0:0] wire_ram_block1a_7portbdataout; wire [0:0] wire_ram_block1a_8portbdataout; wire [0:0] wire_ram_block1a_9portbdataout; wire [0:0] wire_ram_block1a_10portbdataout; wire [0:0] wire_ram_block1a_11portbdataout; wire [0:0] wire_ram_block1a_12portbdataout; wire [0:0] wire_ram_block1a_13portbdataout; wire [0:0] wire_ram_block1a_14portbdataout; wire [0:0] wire_ram_block1a_15portbdataout; wire [0:0] wire_ram_block1a_16portbdataout; wire [0:0] wire_ram_block1a_17portbdataout; wire [0:0] wire_ram_block1a_18portbdataout; wire [0:0] wire_ram_block1a_19portbdataout; wire [0:0] wire_ram_block1a_20portbdataout; wire [0:0] wire_ram_block1a_21portbdataout; wire [0:0] wire_ram_block1a_22portbdataout; wire [0:0] wire_ram_block1a_23portbdataout; wire [0:0] wire_ram_block1a_24portbdataout; wire [0:0] wire_ram_block1a_25portbdataout; wire [0:0] wire_ram_block1a_26portbdataout; wire [0:0] wire_ram_block1a_27portbdataout; wire [0:0] wire_ram_block1a_28portbdataout; wire [0:0] wire_ram_block1a_29portbdataout; wire [0:0] wire_ram_block1a_30portbdataout; wire [0:0] wire_ram_block1a_31portbdataout; wire [9:0] address_a_wire; wire [9:0] address_b_wire; cyclone_ram_block ram_block1a_0 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[0]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_0portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_0.connectivity_checking = "OFF", ram_block1a_0.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_0.init_file_layout = "port_b", ram_block1a_0.logical_ram_name = "ALTSYNCRAM", ram_block1a_0.mem_init0 = 1024'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, ram_block1a_0.mixed_port_feed_through_mode = "old", ram_block1a_0.operation_mode = "dual_port", ram_block1a_0.port_a_address_clear = "none", ram_block1a_0.port_a_address_width = 10, ram_block1a_0.port_a_data_in_clear = "none", ram_block1a_0.port_a_data_width = 1, ram_block1a_0.port_a_first_address = 0, ram_block1a_0.port_a_first_bit_number = 0, ram_block1a_0.port_a_last_address = 1023, ram_block1a_0.port_a_logical_ram_depth = 1024, ram_block1a_0.port_a_logical_ram_width = 32, ram_block1a_0.port_a_write_enable_clear = "none", ram_block1a_0.port_b_address_clear = "none", ram_block1a_0.port_b_address_clock = "clock0", ram_block1a_0.port_b_address_width = 10, ram_block1a_0.port_b_data_out_clear = "none", ram_block1a_0.port_b_data_out_clock = "clock0", ram_block1a_0.port_b_data_width = 1, ram_block1a_0.port_b_first_address = 0, ram_block1a_0.port_b_first_bit_number = 0, ram_block1a_0.port_b_last_address = 1023, ram_block1a_0.port_b_logical_ram_depth = 1024, ram_block1a_0.port_b_logical_ram_width = 32, ram_block1a_0.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_0.power_up_uninitialized = "false", ram_block1a_0.ram_block_type = "M4K", ram_block1a_0.lpm_type = "cyclone_ram_block", ram_block1a_0.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_1 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[1]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_1portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_1.connectivity_checking = "OFF", ram_block1a_1.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_1.init_file_layout = "port_b", ram_block1a_1.logical_ram_name = "ALTSYNCRAM", ram_block1a_1.mem_init0 = 1024'h9999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999, ram_block1a_1.mixed_port_feed_through_mode = "old", ram_block1a_1.operation_mode = "dual_port", ram_block1a_1.port_a_address_clear = "none", ram_block1a_1.port_a_address_width = 10, ram_block1a_1.port_a_data_in_clear = "none", ram_block1a_1.port_a_data_width = 1, ram_block1a_1.port_a_first_address = 0, ram_block1a_1.port_a_first_bit_number = 1, ram_block1a_1.port_a_last_address = 1023, ram_block1a_1.port_a_logical_ram_depth = 1024, ram_block1a_1.port_a_logical_ram_width = 32, ram_block1a_1.port_a_write_enable_clear = "none", ram_block1a_1.port_b_address_clear = "none", ram_block1a_1.port_b_address_clock = "clock0", ram_block1a_1.port_b_address_width = 10, ram_block1a_1.port_b_data_out_clear = "none", ram_block1a_1.port_b_data_out_clock = "clock0", ram_block1a_1.port_b_data_width = 1, ram_block1a_1.port_b_first_address = 0, ram_block1a_1.port_b_first_bit_number = 1, ram_block1a_1.port_b_last_address = 1023, ram_block1a_1.port_b_logical_ram_depth = 1024, ram_block1a_1.port_b_logical_ram_width = 32, ram_block1a_1.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_1.power_up_uninitialized = "false", ram_block1a_1.ram_block_type = "M4K", ram_block1a_1.lpm_type = "cyclone_ram_block", ram_block1a_1.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_2 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[2]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_2portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_2.connectivity_checking = "OFF", ram_block1a_2.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_2.init_file_layout = "port_b", ram_block1a_2.logical_ram_name = "ALTSYNCRAM", ram_block1a_2.mem_init0 = 1024'hB4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4, ram_block1a_2.mixed_port_feed_through_mode = "old", ram_block1a_2.operation_mode = "dual_port", ram_block1a_2.port_a_address_clear = "none", ram_block1a_2.port_a_address_width = 10, ram_block1a_2.port_a_data_in_clear = "none", ram_block1a_2.port_a_data_width = 1, ram_block1a_2.port_a_first_address = 0, ram_block1a_2.port_a_first_bit_number = 2, ram_block1a_2.port_a_last_address = 1023, ram_block1a_2.port_a_logical_ram_depth = 1024, ram_block1a_2.port_a_logical_ram_width = 32, ram_block1a_2.port_a_write_enable_clear = "none", ram_block1a_2.port_b_address_clear = "none", ram_block1a_2.port_b_address_clock = "clock0", ram_block1a_2.port_b_address_width = 10, ram_block1a_2.port_b_data_out_clear = "none", ram_block1a_2.port_b_data_out_clock = "clock0", ram_block1a_2.port_b_data_width = 1, ram_block1a_2.port_b_first_address = 0, ram_block1a_2.port_b_first_bit_number = 2, ram_block1a_2.port_b_last_address = 1023, ram_block1a_2.port_b_logical_ram_depth = 1024, ram_block1a_2.port_b_logical_ram_width = 32, ram_block1a_2.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_2.power_up_uninitialized = "false", ram_block1a_2.ram_block_type = "M4K", ram_block1a_2.lpm_type = "cyclone_ram_block", ram_block1a_2.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_3 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[3]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_3portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_3.connectivity_checking = "OFF", ram_block1a_3.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_3.init_file_layout = "port_b", ram_block1a_3.logical_ram_name = "ALTSYNCRAM", ram_block1a_3.mem_init0 = 1024'h9D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D629D62, ram_block1a_3.mixed_port_feed_through_mode = "old", ram_block1a_3.operation_mode = "dual_port", ram_block1a_3.port_a_address_clear = "none", ram_block1a_3.port_a_address_width = 10, ram_block1a_3.port_a_data_in_clear = "none", ram_block1a_3.port_a_data_width = 1, ram_block1a_3.port_a_first_address = 0, ram_block1a_3.port_a_first_bit_number = 3, ram_block1a_3.port_a_last_address = 1023, ram_block1a_3.port_a_logical_ram_depth = 1024, ram_block1a_3.port_a_logical_ram_width = 32, ram_block1a_3.port_a_write_enable_clear = "none", ram_block1a_3.port_b_address_clear = "none", ram_block1a_3.port_b_address_clock = "clock0", ram_block1a_3.port_b_address_width = 10, ram_block1a_3.port_b_data_out_clear = "none", ram_block1a_3.port_b_data_out_clock = "clock0", ram_block1a_3.port_b_data_width = 1, ram_block1a_3.port_b_first_address = 0, ram_block1a_3.port_b_first_bit_number = 3, ram_block1a_3.port_b_last_address = 1023, ram_block1a_3.port_b_logical_ram_depth = 1024, ram_block1a_3.port_b_logical_ram_width = 32, ram_block1a_3.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_3.power_up_uninitialized = "false", ram_block1a_3.ram_block_type = "M4K", ram_block1a_3.lpm_type = "cyclone_ram_block", ram_block1a_3.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_4 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[4]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_4portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_4.connectivity_checking = "OFF", ram_block1a_4.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_4.init_file_layout = "port_b", ram_block1a_4.logical_ram_name = "ALTSYNCRAM", ram_block1a_4.mem_init0 = 1024'h98FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA670598FA6705, ram_block1a_4.mixed_port_feed_through_mode = "old", ram_block1a_4.operation_mode = "dual_port", ram_block1a_4.port_a_address_clear = "none", ram_block1a_4.port_a_address_width = 10, ram_block1a_4.port_a_data_in_clear = "none", ram_block1a_4.port_a_data_width = 1, ram_block1a_4.port_a_first_address = 0, ram_block1a_4.port_a_first_bit_number = 4, ram_block1a_4.port_a_last_address = 1023, ram_block1a_4.port_a_logical_ram_depth = 1024, ram_block1a_4.port_a_logical_ram_width = 32, ram_block1a_4.port_a_write_enable_clear = "none", ram_block1a_4.port_b_address_clear = "none", ram_block1a_4.port_b_address_clock = "clock0", ram_block1a_4.port_b_address_width = 10, ram_block1a_4.port_b_data_out_clear = "none", ram_block1a_4.port_b_data_out_clock = "clock0", ram_block1a_4.port_b_data_width = 1, ram_block1a_4.port_b_first_address = 0, ram_block1a_4.port_b_first_bit_number = 4, ram_block1a_4.port_b_last_address = 1023, ram_block1a_4.port_b_logical_ram_depth = 1024, ram_block1a_4.port_b_logical_ram_width = 32, ram_block1a_4.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_4.power_up_uninitialized = "false", ram_block1a_4.ram_block_type = "M4K", ram_block1a_4.lpm_type = "cyclone_ram_block", ram_block1a_4.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_5 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[5]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_5portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_5.connectivity_checking = "OFF", ram_block1a_5.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_5.init_file_layout = "port_b", ram_block1a_5.logical_ram_name = "ALTSYNCRAM", ram_block1a_5.mem_init0 = 1024'h2A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E72A1D4D18D5E2B2E7, ram_block1a_5.mixed_port_feed_through_mode = "old", ram_block1a_5.operation_mode = "dual_port", ram_block1a_5.port_a_address_clear = "none", ram_block1a_5.port_a_address_width = 10, ram_block1a_5.port_a_data_in_clear = "none", ram_block1a_5.port_a_data_width = 1, ram_block1a_5.port_a_first_address = 0, ram_block1a_5.port_a_first_bit_number = 5, ram_block1a_5.port_a_last_address = 1023, ram_block1a_5.port_a_logical_ram_depth = 1024, ram_block1a_5.port_a_logical_ram_width = 32, ram_block1a_5.port_a_write_enable_clear = "none", ram_block1a_5.port_b_address_clear = "none", ram_block1a_5.port_b_address_clock = "clock0", ram_block1a_5.port_b_address_width = 10, ram_block1a_5.port_b_data_out_clear = "none", ram_block1a_5.port_b_data_out_clock = "clock0", ram_block1a_5.port_b_data_width = 1, ram_block1a_5.port_b_first_address = 0, ram_block1a_5.port_b_first_bit_number = 5, ram_block1a_5.port_b_last_address = 1023, ram_block1a_5.port_b_logical_ram_depth = 1024, ram_block1a_5.port_b_logical_ram_width = 32, ram_block1a_5.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_5.power_up_uninitialized = "false", ram_block1a_5.ram_block_type = "M4K", ram_block1a_5.lpm_type = "cyclone_ram_block", ram_block1a_5.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_6 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[6]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_6portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_6.connectivity_checking = "OFF", ram_block1a_6.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_6.init_file_layout = "port_b", ram_block1a_6.logical_ram_name = "ALTSYNCRAM", ram_block1a_6.mem_init0 = 1024'hA9CFB99A7C2D0B7D5630466583D2F482A9CFB99A7C2D0B7D5630466583D2F482A9CFB99A7C2D0B7D5630466583D2F482A9CFB99A7C2D0B7D5630466583D2F482A9CFB99A7C2D0B7D5630466583D2F482A9CFB99A7C2D0B7D5630466583D2F482A9CFB99A7C2D0B7D5630466583D2F482A9CFB99A7C2D0B7D5630466583D2F482, ram_block1a_6.mixed_port_feed_through_mode = "old", ram_block1a_6.operation_mode = "dual_port", ram_block1a_6.port_a_address_clear = "none", ram_block1a_6.port_a_address_width = 10, ram_block1a_6.port_a_data_in_clear = "none", ram_block1a_6.port_a_data_width = 1, ram_block1a_6.port_a_first_address = 0, ram_block1a_6.port_a_first_bit_number = 6, ram_block1a_6.port_a_last_address = 1023, ram_block1a_6.port_a_logical_ram_depth = 1024, ram_block1a_6.port_a_logical_ram_width = 32, ram_block1a_6.port_a_write_enable_clear = "none", ram_block1a_6.port_b_address_clear = "none", ram_block1a_6.port_b_address_clock = "clock0", ram_block1a_6.port_b_address_width = 10, ram_block1a_6.port_b_data_out_clear = "none", ram_block1a_6.port_b_data_out_clock = "clock0", ram_block1a_6.port_b_data_width = 1, ram_block1a_6.port_b_first_address = 0, ram_block1a_6.port_b_first_bit_number = 6, ram_block1a_6.port_b_last_address = 1023, ram_block1a_6.port_b_logical_ram_depth = 1024, ram_block1a_6.port_b_logical_ram_width = 32, ram_block1a_6.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_6.power_up_uninitialized = "false", ram_block1a_6.ram_block_type = "M4K", ram_block1a_6.lpm_type = "cyclone_ram_block", ram_block1a_6.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_7 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[7]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_7portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_7.connectivity_checking = "OFF", ram_block1a_7.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_7.init_file_layout = "port_b", ram_block1a_7.logical_ram_name = "ALTSYNCRAM", ram_block1a_7.mem_init0 = 1024'hD743B160D636E6508173F70555E412D228BC4E9F29C919AF7E8C08FAAA1BED2DD743B160D636E6508173F70555E412D228BC4E9F29C919AF7E8C08FAAA1BED2DD743B160D636E6508173F70555E412D228BC4E9F29C919AF7E8C08FAAA1BED2DD743B160D636E6508173F70555E412D228BC4E9F29C919AF7E8C08FAAA1BED2D, ram_block1a_7.mixed_port_feed_through_mode = "old", ram_block1a_7.operation_mode = "dual_port", ram_block1a_7.port_a_address_clear = "none", ram_block1a_7.port_a_address_width = 10, ram_block1a_7.port_a_data_in_clear = "none", ram_block1a_7.port_a_data_width = 1, ram_block1a_7.port_a_first_address = 0, ram_block1a_7.port_a_first_bit_number = 7, ram_block1a_7.port_a_last_address = 1023, ram_block1a_7.port_a_logical_ram_depth = 1024, ram_block1a_7.port_a_logical_ram_width = 32, ram_block1a_7.port_a_write_enable_clear = "none", ram_block1a_7.port_b_address_clear = "none", ram_block1a_7.port_b_address_clock = "clock0", ram_block1a_7.port_b_address_width = 10, ram_block1a_7.port_b_data_out_clear = "none", ram_block1a_7.port_b_data_out_clock = "clock0", ram_block1a_7.port_b_data_width = 1, ram_block1a_7.port_b_first_address = 0, ram_block1a_7.port_b_first_bit_number = 7, ram_block1a_7.port_b_last_address = 1023, ram_block1a_7.port_b_logical_ram_depth = 1024, ram_block1a_7.port_b_logical_ram_width = 32, ram_block1a_7.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_7.power_up_uninitialized = "false", ram_block1a_7.ram_block_type = "M4K", ram_block1a_7.lpm_type = "cyclone_ram_block", ram_block1a_7.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_8 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[8]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_8portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_8.connectivity_checking = "OFF", ram_block1a_8.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_8.init_file_layout = "port_b", ram_block1a_8.logical_ram_name = "ALTSYNCRAM", ram_block1a_8.mem_init0 = 1024'h92F09FFCF5F7EA9AC7958CACA162AF4DBA4CD163DC3EF335B91984560B7942606D0F60030A081565386A73535E9D50B245B32E9C23C10CCA46E67BA9F486BD9F92F09FFCF5F7EA9AC7958CACA162AF4DBA4CD163DC3EF335B91984560B7942606D0F60030A081565386A73535E9D50B245B32E9C23C10CCA46E67BA9F486BD9F, ram_block1a_8.mixed_port_feed_through_mode = "old", ram_block1a_8.operation_mode = "dual_port", ram_block1a_8.port_a_address_clear = "none", ram_block1a_8.port_a_address_width = 10, ram_block1a_8.port_a_data_in_clear = "none", ram_block1a_8.port_a_data_width = 1, ram_block1a_8.port_a_first_address = 0, ram_block1a_8.port_a_first_bit_number = 8, ram_block1a_8.port_a_last_address = 1023, ram_block1a_8.port_a_logical_ram_depth = 1024, ram_block1a_8.port_a_logical_ram_width = 32, ram_block1a_8.port_a_write_enable_clear = "none", ram_block1a_8.port_b_address_clear = "none", ram_block1a_8.port_b_address_clock = "clock0", ram_block1a_8.port_b_address_width = 10, ram_block1a_8.port_b_data_out_clear = "none", ram_block1a_8.port_b_data_out_clock = "clock0", ram_block1a_8.port_b_data_width = 1, ram_block1a_8.port_b_first_address = 0, ram_block1a_8.port_b_first_bit_number = 8, ram_block1a_8.port_b_last_address = 1023, ram_block1a_8.port_b_logical_ram_depth = 1024, ram_block1a_8.port_b_logical_ram_width = 32, ram_block1a_8.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_8.power_up_uninitialized = "false", ram_block1a_8.ram_block_type = "M4K", ram_block1a_8.lpm_type = "cyclone_ram_block", ram_block1a_8.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_9 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[9]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_9portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_9.connectivity_checking = "OFF", ram_block1a_9.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_9.init_file_layout = "port_b", ram_block1a_9.logical_ram_name = "ALTSYNCRAM", ram_block1a_9.mem_init0 = 1024'h34AE14707DA54A5F428863464FD66C2949F7012620F80E2F2FD53641109A795C59A1747377AD5F3A7AE21015114B3C9B0C442FBA033902E569334DE8E41CC4C3CB51EB8F825AB5A0BD779CB9B02993D6B608FED9DF07F1D0D02AC9BEEF6586A3A65E8B8C8852A0C5851DEFEAEEB4C364F3BBD045FCC6FD1A96CCB2171BE33B3C, ram_block1a_9.mixed_port_feed_through_mode = "old", ram_block1a_9.operation_mode = "dual_port", ram_block1a_9.port_a_address_clear = "none", ram_block1a_9.port_a_address_width = 10, ram_block1a_9.port_a_data_in_clear = "none", ram_block1a_9.port_a_data_width = 1, ram_block1a_9.port_a_first_address = 0, ram_block1a_9.port_a_first_bit_number = 9, ram_block1a_9.port_a_last_address = 1023, ram_block1a_9.port_a_logical_ram_depth = 1024, ram_block1a_9.port_a_logical_ram_width = 32, ram_block1a_9.port_a_write_enable_clear = "none", ram_block1a_9.port_b_address_clear = "none", ram_block1a_9.port_b_address_clock = "clock0", ram_block1a_9.port_b_address_width = 10, ram_block1a_9.port_b_data_out_clear = "none", ram_block1a_9.port_b_data_out_clock = "clock0", ram_block1a_9.port_b_data_width = 1, ram_block1a_9.port_b_first_address = 0, ram_block1a_9.port_b_first_bit_number = 9, ram_block1a_9.port_b_last_address = 1023, ram_block1a_9.port_b_logical_ram_depth = 1024, ram_block1a_9.port_b_logical_ram_width = 32, ram_block1a_9.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_9.power_up_uninitialized = "false", ram_block1a_9.ram_block_type = "M4K", ram_block1a_9.lpm_type = "cyclone_ram_block", ram_block1a_9.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_10 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[10]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_10portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_10.connectivity_checking = "OFF", ram_block1a_10.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_10.init_file_layout = "port_b", ram_block1a_10.logical_ram_name = "ALTSYNCRAM", ram_block1a_10.mem_init0 = 1024'h1BECB4CC84C43CCE64C1EBF7BBAA35D3618AC6F8B7AF1AD86AA7CC95988057B407B8819AD3997CBB09F6AEB3FEF6701430DFBD35E1FB4F4D7FD0D06829D18662D0BD5F43069E896ED9B6774E0B83A605D782382168A8EB08BA8D052B77E5D117A1E60A165BCBDC7E8CEB41591042B370C3646D701D3DB257E91C627F3232BD5E, ram_block1a_10.mixed_port_feed_through_mode = "old", ram_block1a_10.operation_mode = "dual_port", ram_block1a_10.port_a_address_clear = "none", ram_block1a_10.port_a_address_width = 10, ram_block1a_10.port_a_data_in_clear = "none", ram_block1a_10.port_a_data_width = 1, ram_block1a_10.port_a_first_address = 0, ram_block1a_10.port_a_first_bit_number = 10, ram_block1a_10.port_a_last_address = 1023, ram_block1a_10.port_a_logical_ram_depth = 1024, ram_block1a_10.port_a_logical_ram_width = 32, ram_block1a_10.port_a_write_enable_clear = "none", ram_block1a_10.port_b_address_clear = "none", ram_block1a_10.port_b_address_clock = "clock0", ram_block1a_10.port_b_address_width = 10, ram_block1a_10.port_b_data_out_clear = "none", ram_block1a_10.port_b_data_out_clock = "clock0", ram_block1a_10.port_b_data_width = 1, ram_block1a_10.port_b_first_address = 0, ram_block1a_10.port_b_first_bit_number = 10, ram_block1a_10.port_b_last_address = 1023, ram_block1a_10.port_b_logical_ram_depth = 1024, ram_block1a_10.port_b_logical_ram_width = 32, ram_block1a_10.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_10.power_up_uninitialized = "false", ram_block1a_10.ram_block_type = "M4K", ram_block1a_10.lpm_type = "cyclone_ram_block", ram_block1a_10.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_11 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[11]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_11portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_11.connectivity_checking = "OFF", ram_block1a_11.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_11.init_file_layout = "port_b", ram_block1a_11.logical_ram_name = "ALTSYNCRAM", ram_block1a_11.mem_init0 = 1024'h694AE634DD122399EF466F1E0435F4B53465993BD2150C94E84D473328189BBD1F689414BD38459BC503483C635397921303971DA0777AE28E2E25687E7E2CCDFC0EF8628A5DF7EC23252E43516123E4F730F46FCF40B8C12D10134C1A284EEBEA7BCB45E02F908A145F5C21360641A785768208E9269FA55B77522A39094084, ram_block1a_11.mixed_port_feed_through_mode = "old", ram_block1a_11.operation_mode = "dual_port", ram_block1a_11.port_a_address_clear = "none", ram_block1a_11.port_a_address_width = 10, ram_block1a_11.port_a_data_in_clear = "none", ram_block1a_11.port_a_data_width = 1, ram_block1a_11.port_a_first_address = 0, ram_block1a_11.port_a_first_bit_number = 11, ram_block1a_11.port_a_last_address = 1023, ram_block1a_11.port_a_logical_ram_depth = 1024, ram_block1a_11.port_a_logical_ram_width = 32, ram_block1a_11.port_a_write_enable_clear = "none", ram_block1a_11.port_b_address_clear = "none", ram_block1a_11.port_b_address_clock = "clock0", ram_block1a_11.port_b_address_width = 10, ram_block1a_11.port_b_data_out_clear = "none", ram_block1a_11.port_b_data_out_clock = "clock0", ram_block1a_11.port_b_data_width = 1, ram_block1a_11.port_b_first_address = 0, ram_block1a_11.port_b_first_bit_number = 11, ram_block1a_11.port_b_last_address = 1023, ram_block1a_11.port_b_logical_ram_depth = 1024, ram_block1a_11.port_b_logical_ram_width = 32, ram_block1a_11.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_11.power_up_uninitialized = "false", ram_block1a_11.ram_block_type = "M4K", ram_block1a_11.lpm_type = "cyclone_ram_block", ram_block1a_11.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_12 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[12]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_12portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_12.connectivity_checking = "OFF", ram_block1a_12.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_12.init_file_layout = "port_b", ram_block1a_12.logical_ram_name = "ALTSYNCRAM", ram_block1a_12.mem_init0 = 1024'hC94440383327EA6780E37B6ABEA84E1F1F6CBB1EE307144E5AC38D4664ADB73EE2496D173C228368ADEC5767F1C761313043B037FE485B1171CD80122FE6AF412E622A4802490C30A2E55C18DCDA7E68FB4FFC689D74D63C7CE0AF3900FBC04E312D15614F56201F8A823115D6F01367C604C344907FFD3713ABE1360DD4CD66, ram_block1a_12.mixed_port_feed_through_mode = "old", ram_block1a_12.operation_mode = "dual_port", ram_block1a_12.port_a_address_clear = "none", ram_block1a_12.port_a_address_width = 10, ram_block1a_12.port_a_data_in_clear = "none", ram_block1a_12.port_a_data_width = 1, ram_block1a_12.port_a_first_address = 0, ram_block1a_12.port_a_first_bit_number = 12, ram_block1a_12.port_a_last_address = 1023, ram_block1a_12.port_a_logical_ram_depth = 1024, ram_block1a_12.port_a_logical_ram_width = 32, ram_block1a_12.port_a_write_enable_clear = "none", ram_block1a_12.port_b_address_clear = "none", ram_block1a_12.port_b_address_clock = "clock0", ram_block1a_12.port_b_address_width = 10, ram_block1a_12.port_b_data_out_clear = "none", ram_block1a_12.port_b_data_out_clock = "clock0", ram_block1a_12.port_b_data_width = 1, ram_block1a_12.port_b_first_address = 0, ram_block1a_12.port_b_first_bit_number = 12, ram_block1a_12.port_b_last_address = 1023, ram_block1a_12.port_b_logical_ram_depth = 1024, ram_block1a_12.port_b_logical_ram_width = 32, ram_block1a_12.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_12.power_up_uninitialized = "false", ram_block1a_12.ram_block_type = "M4K", ram_block1a_12.lpm_type = "cyclone_ram_block", ram_block1a_12.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_13 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[13]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_13portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_13.connectivity_checking = "OFF", ram_block1a_13.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_13.init_file_layout = "port_b", ram_block1a_13.logical_ram_name = "ALTSYNCRAM", ram_block1a_13.mem_init0 = 1024'h4D04D5EE331DE2D26A737F28E39E98B9D48B3EBC7EB2A683BFDCAB702C317BC899200AE4ED3815F7B552890070D44B940685E894A0D73FAF68FD7955F15AB594470BD2910D78CBDE657A57058EF197E51BA476E15FFE698EB6D0A475037E07B7942B25B9925319DC9B7D842D5AD864CFFD8D97E88DDCB6A447F2365EDC77D89E, ram_block1a_13.mixed_port_feed_through_mode = "old", ram_block1a_13.operation_mode = "dual_port", ram_block1a_13.port_a_address_clear = "none", ram_block1a_13.port_a_address_width = 10, ram_block1a_13.port_a_data_in_clear = "none", ram_block1a_13.port_a_data_width = 1, ram_block1a_13.port_a_first_address = 0, ram_block1a_13.port_a_first_bit_number = 13, ram_block1a_13.port_a_last_address = 1023, ram_block1a_13.port_a_logical_ram_depth = 1024, ram_block1a_13.port_a_logical_ram_width = 32, ram_block1a_13.port_a_write_enable_clear = "none", ram_block1a_13.port_b_address_clear = "none", ram_block1a_13.port_b_address_clock = "clock0", ram_block1a_13.port_b_address_width = 10, ram_block1a_13.port_b_data_out_clear = "none", ram_block1a_13.port_b_data_out_clock = "clock0", ram_block1a_13.port_b_data_width = 1, ram_block1a_13.port_b_first_address = 0, ram_block1a_13.port_b_first_bit_number = 13, ram_block1a_13.port_b_last_address = 1023, ram_block1a_13.port_b_logical_ram_depth = 1024, ram_block1a_13.port_b_logical_ram_width = 32, ram_block1a_13.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_13.power_up_uninitialized = "false", ram_block1a_13.ram_block_type = "M4K", ram_block1a_13.lpm_type = "cyclone_ram_block", ram_block1a_13.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_14 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[14]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_14portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_14.connectivity_checking = "OFF", ram_block1a_14.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_14.init_file_layout = "port_b", ram_block1a_14.logical_ram_name = "ALTSYNCRAM", ram_block1a_14.mem_init0 = 1024'h9B3CB9E0842598F7A5345B4E885F331B53BCAD8BEB535D736493F56D25AA91DE86B7C3B8C7AFDD87BF9A8B1657B80042DE1B1DD3E4BC7603AB1CD53D794665864F1A61EC6A4067D67215AD467633E6628A953BF71432C652B2BE234DD4C977F45095149C37E5078647BA5D36AB9DD630C13AE8A61B9D202A5E33011E876EDFA5, ram_block1a_14.mixed_port_feed_through_mode = "old", ram_block1a_14.operation_mode = "dual_port", ram_block1a_14.port_a_address_clear = "none", ram_block1a_14.port_a_address_width = 10, ram_block1a_14.port_a_data_in_clear = "none", ram_block1a_14.port_a_data_width = 1, ram_block1a_14.port_a_first_address = 0, ram_block1a_14.port_a_first_bit_number = 14, ram_block1a_14.port_a_last_address = 1023, ram_block1a_14.port_a_logical_ram_depth = 1024, ram_block1a_14.port_a_logical_ram_width = 32, ram_block1a_14.port_a_write_enable_clear = "none", ram_block1a_14.port_b_address_clear = "none", ram_block1a_14.port_b_address_clock = "clock0", ram_block1a_14.port_b_address_width = 10, ram_block1a_14.port_b_data_out_clear = "none", ram_block1a_14.port_b_data_out_clock = "clock0", ram_block1a_14.port_b_data_width = 1, ram_block1a_14.port_b_first_address = 0, ram_block1a_14.port_b_first_bit_number = 14, ram_block1a_14.port_b_last_address = 1023, ram_block1a_14.port_b_logical_ram_depth = 1024, ram_block1a_14.port_b_logical_ram_width = 32, ram_block1a_14.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_14.power_up_uninitialized = "false", ram_block1a_14.ram_block_type = "M4K", ram_block1a_14.lpm_type = "cyclone_ram_block", ram_block1a_14.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_15 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[15]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_15portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_15.connectivity_checking = "OFF", ram_block1a_15.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_15.init_file_layout = "port_b", ram_block1a_15.logical_ram_name = "ALTSYNCRAM", ram_block1a_15.mem_init0 = 1024'h5D6BB1E38D939FF9725C031EDBD83217C910282D0545ACA811F8EF4562837A7C85E3DD88E3ED1B7DB3FDAD7D2DACA3DA1938560E203D0F2CC4FF912E1811CFF094C283B34879A8A8AFF3F746025B843ECCB70A15BECB1EF90C769D151F6C4C045A4CB9D87E0A692C5E72890D280305AA57B6E46F9492FF5D3D7EE37D319E4580, ram_block1a_15.mixed_port_feed_through_mode = "old", ram_block1a_15.operation_mode = "dual_port", ram_block1a_15.port_a_address_clear = "none", ram_block1a_15.port_a_address_width = 10, ram_block1a_15.port_a_data_in_clear = "none", ram_block1a_15.port_a_data_width = 1, ram_block1a_15.port_a_first_address = 0, ram_block1a_15.port_a_first_bit_number = 15, ram_block1a_15.port_a_last_address = 1023, ram_block1a_15.port_a_logical_ram_depth = 1024, ram_block1a_15.port_a_logical_ram_width = 32, ram_block1a_15.port_a_write_enable_clear = "none", ram_block1a_15.port_b_address_clear = "none", ram_block1a_15.port_b_address_clock = "clock0", ram_block1a_15.port_b_address_width = 10, ram_block1a_15.port_b_data_out_clear = "none", ram_block1a_15.port_b_data_out_clock = "clock0", ram_block1a_15.port_b_data_width = 1, ram_block1a_15.port_b_first_address = 0, ram_block1a_15.port_b_first_bit_number = 15, ram_block1a_15.port_b_last_address = 1023, ram_block1a_15.port_b_logical_ram_depth = 1024, ram_block1a_15.port_b_logical_ram_width = 32, ram_block1a_15.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_15.power_up_uninitialized = "false", ram_block1a_15.ram_block_type = "M4K", ram_block1a_15.lpm_type = "cyclone_ram_block", ram_block1a_15.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_16 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[16]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_16portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_16.connectivity_checking = "OFF", ram_block1a_16.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_16.init_file_layout = "port_b", ram_block1a_16.logical_ram_name = "ALTSYNCRAM", ram_block1a_16.mem_init0 = 1024'h8C5DCB0415A525568A4496270C92241AD25C7FEE9E21CEF43651A89B5C0AEBFB37D1CD366AB2EDFCD73F8D834A32838AF1586196A266045E3AAE0F74A65A482254F4A76FFE1994D35BCC4C14AB6531FF02D003CDA15F4D20E65C96F042B27E7733F6D31DD5645C79E736F3F861E5062E68D5AF8DBC30258A7BA7435F8020C9A6, ram_block1a_16.mixed_port_feed_through_mode = "old", ram_block1a_16.operation_mode = "dual_port", ram_block1a_16.port_a_address_clear = "none", ram_block1a_16.port_a_address_width = 10, ram_block1a_16.port_a_data_in_clear = "none", ram_block1a_16.port_a_data_width = 1, ram_block1a_16.port_a_first_address = 0, ram_block1a_16.port_a_first_bit_number = 16, ram_block1a_16.port_a_last_address = 1023, ram_block1a_16.port_a_logical_ram_depth = 1024, ram_block1a_16.port_a_logical_ram_width = 32, ram_block1a_16.port_a_write_enable_clear = "none", ram_block1a_16.port_b_address_clear = "none", ram_block1a_16.port_b_address_clock = "clock0", ram_block1a_16.port_b_address_width = 10, ram_block1a_16.port_b_data_out_clear = "none", ram_block1a_16.port_b_data_out_clock = "clock0", ram_block1a_16.port_b_data_width = 1, ram_block1a_16.port_b_first_address = 0, ram_block1a_16.port_b_first_bit_number = 16, ram_block1a_16.port_b_last_address = 1023, ram_block1a_16.port_b_logical_ram_depth = 1024, ram_block1a_16.port_b_logical_ram_width = 32, ram_block1a_16.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_16.power_up_uninitialized = "false", ram_block1a_16.ram_block_type = "M4K", ram_block1a_16.lpm_type = "cyclone_ram_block", ram_block1a_16.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_17 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[17]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_17portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_17.connectivity_checking = "OFF", ram_block1a_17.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_17.init_file_layout = "port_b", ram_block1a_17.logical_ram_name = "ALTSYNCRAM", ram_block1a_17.mem_init0 = 1024'h7931354E8665C31844853113433F13F1684E38EAFDBD48D0C6AAFFCCE7E2C82CEF2CABA918A40CB8F050F9CA3724A06C0B2455DAD687B02D9095724FAC76038612BC5B1FF0C68A36D9FEEA96835EA4445BC27291C098807ECA545E690712FA71882DD1DA111BC5167CA23C67F5E5921978ACB399D7ECD8030D66A7C14ED6B453, ram_block1a_17.mixed_port_feed_through_mode = "old", ram_block1a_17.operation_mode = "dual_port", ram_block1a_17.port_a_address_clear = "none", ram_block1a_17.port_a_address_width = 10, ram_block1a_17.port_a_data_in_clear = "none", ram_block1a_17.port_a_data_width = 1, ram_block1a_17.port_a_first_address = 0, ram_block1a_17.port_a_first_bit_number = 17, ram_block1a_17.port_a_last_address = 1023, ram_block1a_17.port_a_logical_ram_depth = 1024, ram_block1a_17.port_a_logical_ram_width = 32, ram_block1a_17.port_a_write_enable_clear = "none", ram_block1a_17.port_b_address_clear = "none", ram_block1a_17.port_b_address_clock = "clock0", ram_block1a_17.port_b_address_width = 10, ram_block1a_17.port_b_data_out_clear = "none", ram_block1a_17.port_b_data_out_clock = "clock0", ram_block1a_17.port_b_data_width = 1, ram_block1a_17.port_b_first_address = 0, ram_block1a_17.port_b_first_bit_number = 17, ram_block1a_17.port_b_last_address = 1023, ram_block1a_17.port_b_logical_ram_depth = 1024, ram_block1a_17.port_b_logical_ram_width = 32, ram_block1a_17.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_17.power_up_uninitialized = "false", ram_block1a_17.ram_block_type = "M4K", ram_block1a_17.lpm_type = "cyclone_ram_block", ram_block1a_17.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_18 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[18]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_18portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_18.connectivity_checking = "OFF", ram_block1a_18.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_18.init_file_layout = "port_b", ram_block1a_18.logical_ram_name = "ALTSYNCRAM", ram_block1a_18.mem_init0 = 1024'h8FC0DE72DBAC8B0ABB020960406DBED5428E067BDF67A3FB051F72692E9831CE9FFA32CD73E09797E8F9B2FBF1EE6BACB47A484D0693FB16A19AACBAE8AB8CD3C72FB96BA8B2FA5FFC697D430BE9D533FC9396B72B8624D9AC2501103AB337CAD9944FB56D7FAF623ACA1E79F8EBB21F696B30B9EF5034988D966E63BC1008DF, ram_block1a_18.mixed_port_feed_through_mode = "old", ram_block1a_18.operation_mode = "dual_port", ram_block1a_18.port_a_address_clear = "none", ram_block1a_18.port_a_address_width = 10, ram_block1a_18.port_a_data_in_clear = "none", ram_block1a_18.port_a_data_width = 1, ram_block1a_18.port_a_first_address = 0, ram_block1a_18.port_a_first_bit_number = 18, ram_block1a_18.port_a_last_address = 1023, ram_block1a_18.port_a_logical_ram_depth = 1024, ram_block1a_18.port_a_logical_ram_width = 32, ram_block1a_18.port_a_write_enable_clear = "none", ram_block1a_18.port_b_address_clear = "none", ram_block1a_18.port_b_address_clock = "clock0", ram_block1a_18.port_b_address_width = 10, ram_block1a_18.port_b_data_out_clear = "none", ram_block1a_18.port_b_data_out_clock = "clock0", ram_block1a_18.port_b_data_width = 1, ram_block1a_18.port_b_first_address = 0, ram_block1a_18.port_b_first_bit_number = 18, ram_block1a_18.port_b_last_address = 1023, ram_block1a_18.port_b_logical_ram_depth = 1024, ram_block1a_18.port_b_logical_ram_width = 32, ram_block1a_18.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_18.power_up_uninitialized = "false", ram_block1a_18.ram_block_type = "M4K", ram_block1a_18.lpm_type = "cyclone_ram_block", ram_block1a_18.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_19 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[19]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_19portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_19.connectivity_checking = "OFF", ram_block1a_19.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_19.init_file_layout = "port_b", ram_block1a_19.logical_ram_name = "ALTSYNCRAM", ram_block1a_19.mem_init0 = 1024'h22DDC7CEAC270E2012E6B3142B4095D5B008E21951A2092235F6943344F067FC9CC4708646C25DA288CAB66832C7F5A819CA62AD97720B84BEF636D33FA337E19D27E5C15FC71F15F20F8167EEE7EA6045D0E9755E31E2E080EC388F2E9FDB67D2EBC96F6F50A2FD55A79B464B9E26D3C7F1F612BAFC1F3D511107C1AE107289, ram_block1a_19.mixed_port_feed_through_mode = "old", ram_block1a_19.operation_mode = "dual_port", ram_block1a_19.port_a_address_clear = "none", ram_block1a_19.port_a_address_width = 10, ram_block1a_19.port_a_data_in_clear = "none", ram_block1a_19.port_a_data_width = 1, ram_block1a_19.port_a_first_address = 0, ram_block1a_19.port_a_first_bit_number = 19, ram_block1a_19.port_a_last_address = 1023, ram_block1a_19.port_a_logical_ram_depth = 1024, ram_block1a_19.port_a_logical_ram_width = 32, ram_block1a_19.port_a_write_enable_clear = "none", ram_block1a_19.port_b_address_clear = "none", ram_block1a_19.port_b_address_clock = "clock0", ram_block1a_19.port_b_address_width = 10, ram_block1a_19.port_b_data_out_clear = "none", ram_block1a_19.port_b_data_out_clock = "clock0", ram_block1a_19.port_b_data_width = 1, ram_block1a_19.port_b_first_address = 0, ram_block1a_19.port_b_first_bit_number = 19, ram_block1a_19.port_b_last_address = 1023, ram_block1a_19.port_b_logical_ram_depth = 1024, ram_block1a_19.port_b_logical_ram_width = 32, ram_block1a_19.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_19.power_up_uninitialized = "false", ram_block1a_19.ram_block_type = "M4K", ram_block1a_19.lpm_type = "cyclone_ram_block", ram_block1a_19.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_20 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[20]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_20portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_20.connectivity_checking = "OFF", ram_block1a_20.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_20.init_file_layout = "port_b", ram_block1a_20.logical_ram_name = "ALTSYNCRAM", ram_block1a_20.mem_init0 = 1024'hB14535817087F4430FF6A944BDF85B2B598C45473C9A5DB910F3DF4D867842D50E4CD4EEF37712F374123EB53E9F7B9601B2A70A1D99DFC91F7DAFE66AF8707E78D1D510EF17F634C07F4BF5C02B6F8F55B3D08EA79D138CFF34ACCA6A1E530D5EFE24FE3EA55D13D3CA38EFF5ABE62B105F7B22808D7338DB56E4FFBD32FECD, ram_block1a_20.mixed_port_feed_through_mode = "old", ram_block1a_20.operation_mode = "dual_port", ram_block1a_20.port_a_address_clear = "none", ram_block1a_20.port_a_address_width = 10, ram_block1a_20.port_a_data_in_clear = "none", ram_block1a_20.port_a_data_width = 1, ram_block1a_20.port_a_first_address = 0, ram_block1a_20.port_a_first_bit_number = 20, ram_block1a_20.port_a_last_address = 1023, ram_block1a_20.port_a_logical_ram_depth = 1024, ram_block1a_20.port_a_logical_ram_width = 32, ram_block1a_20.port_a_write_enable_clear = "none", ram_block1a_20.port_b_address_clear = "none", ram_block1a_20.port_b_address_clock = "clock0", ram_block1a_20.port_b_address_width = 10, ram_block1a_20.port_b_data_out_clear = "none", ram_block1a_20.port_b_data_out_clock = "clock0", ram_block1a_20.port_b_data_width = 1, ram_block1a_20.port_b_first_address = 0, ram_block1a_20.port_b_first_bit_number = 20, ram_block1a_20.port_b_last_address = 1023, ram_block1a_20.port_b_logical_ram_depth = 1024, ram_block1a_20.port_b_logical_ram_width = 32, ram_block1a_20.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_20.power_up_uninitialized = "false", ram_block1a_20.ram_block_type = "M4K", ram_block1a_20.lpm_type = "cyclone_ram_block", ram_block1a_20.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_21 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[21]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_21portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_21.connectivity_checking = "OFF", ram_block1a_21.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_21.init_file_layout = "port_b", ram_block1a_21.logical_ram_name = "ALTSYNCRAM", ram_block1a_21.mem_init0 = 1024'hF74B88B41A2A91915D41624C746D1C14E6DA7D7653A26526FC7AA602FE1AF4C2C35FFAB8266AF8F6656DF4D8ABC7675F4F019CCEDF535E017D82B56DFC642FDEEE35EA6D722913D1184672C6E1ED5EB2949B694D55C08970D014B2CFB4C8F18383741D34D86E3D5796A6F7B6681519296DAB5D2C8B7565F6AA979C760D6C6E68, ram_block1a_21.mixed_port_feed_through_mode = "old", ram_block1a_21.operation_mode = "dual_port", ram_block1a_21.port_a_address_clear = "none", ram_block1a_21.port_a_address_width = 10, ram_block1a_21.port_a_data_in_clear = "none", ram_block1a_21.port_a_data_width = 1, ram_block1a_21.port_a_first_address = 0, ram_block1a_21.port_a_first_bit_number = 21, ram_block1a_21.port_a_last_address = 1023, ram_block1a_21.port_a_logical_ram_depth = 1024, ram_block1a_21.port_a_logical_ram_width = 32, ram_block1a_21.port_a_write_enable_clear = "none", ram_block1a_21.port_b_address_clear = "none", ram_block1a_21.port_b_address_clock = "clock0", ram_block1a_21.port_b_address_width = 10, ram_block1a_21.port_b_data_out_clear = "none", ram_block1a_21.port_b_data_out_clock = "clock0", ram_block1a_21.port_b_data_width = 1, ram_block1a_21.port_b_first_address = 0, ram_block1a_21.port_b_first_bit_number = 21, ram_block1a_21.port_b_last_address = 1023, ram_block1a_21.port_b_logical_ram_depth = 1024, ram_block1a_21.port_b_logical_ram_width = 32, ram_block1a_21.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_21.power_up_uninitialized = "false", ram_block1a_21.ram_block_type = "M4K", ram_block1a_21.lpm_type = "cyclone_ram_block", ram_block1a_21.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_22 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[22]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_22portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_22.connectivity_checking = "OFF", ram_block1a_22.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_22.init_file_layout = "port_b", ram_block1a_22.logical_ram_name = "ALTSYNCRAM", ram_block1a_22.mem_init0 = 1024'h28E1CDCF25087888B192C7CBBB4ED274523571DDCC3C1BC263707DAF3ED22497B3DF2D808E3F887CFA5F441086643EAC2A0B833F2D37AB3CE118093DA3974252C87C6CB6C9F9C39F3F68A4A501305BE81B5F6494903D94211E308A39845C083A2C640D833EAC52AC254B409C8CEEA3D5654B25A81374AD8FFA6DFC555AEF4DDB, ram_block1a_22.mixed_port_feed_through_mode = "old", ram_block1a_22.operation_mode = "dual_port", ram_block1a_22.port_a_address_clear = "none", ram_block1a_22.port_a_address_width = 10, ram_block1a_22.port_a_data_in_clear = "none", ram_block1a_22.port_a_data_width = 1, ram_block1a_22.port_a_first_address = 0, ram_block1a_22.port_a_first_bit_number = 22, ram_block1a_22.port_a_last_address = 1023, ram_block1a_22.port_a_logical_ram_depth = 1024, ram_block1a_22.port_a_logical_ram_width = 32, ram_block1a_22.port_a_write_enable_clear = "none", ram_block1a_22.port_b_address_clear = "none", ram_block1a_22.port_b_address_clock = "clock0", ram_block1a_22.port_b_address_width = 10, ram_block1a_22.port_b_data_out_clear = "none", ram_block1a_22.port_b_data_out_clock = "clock0", ram_block1a_22.port_b_data_width = 1, ram_block1a_22.port_b_first_address = 0, ram_block1a_22.port_b_first_bit_number = 22, ram_block1a_22.port_b_last_address = 1023, ram_block1a_22.port_b_logical_ram_depth = 1024, ram_block1a_22.port_b_logical_ram_width = 32, ram_block1a_22.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_22.power_up_uninitialized = "false", ram_block1a_22.ram_block_type = "M4K", ram_block1a_22.lpm_type = "cyclone_ram_block", ram_block1a_22.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_23 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[23]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_23portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_23.connectivity_checking = "OFF", ram_block1a_23.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_23.init_file_layout = "port_b", ram_block1a_23.logical_ram_name = "ALTSYNCRAM", ram_block1a_23.mem_init0 = 1024'hD6BB3978EEEB252FCC1BD2676E0B5D220998D9E64302A34EECE524F72ACD85B4D882D8E094ED4487B306F75DF33F843B274EED7400DFC7880AE271854A0E5D786F982B224B408CE74F9BA7BDCB1A7B73135199114C846B8D2D90055CEDBDE578716D5B4931E7ADEB89B8757D9ED49E03A557EC57F9885E3B1D04D4D4E7A8E9C5, ram_block1a_23.mixed_port_feed_through_mode = "old", ram_block1a_23.operation_mode = "dual_port", ram_block1a_23.port_a_address_clear = "none", ram_block1a_23.port_a_address_width = 10, ram_block1a_23.port_a_data_in_clear = "none", ram_block1a_23.port_a_data_width = 1, ram_block1a_23.port_a_first_address = 0, ram_block1a_23.port_a_first_bit_number = 23, ram_block1a_23.port_a_last_address = 1023, ram_block1a_23.port_a_logical_ram_depth = 1024, ram_block1a_23.port_a_logical_ram_width = 32, ram_block1a_23.port_a_write_enable_clear = "none", ram_block1a_23.port_b_address_clear = "none", ram_block1a_23.port_b_address_clock = "clock0", ram_block1a_23.port_b_address_width = 10, ram_block1a_23.port_b_data_out_clear = "none", ram_block1a_23.port_b_data_out_clock = "clock0", ram_block1a_23.port_b_data_width = 1, ram_block1a_23.port_b_first_address = 0, ram_block1a_23.port_b_first_bit_number = 23, ram_block1a_23.port_b_last_address = 1023, ram_block1a_23.port_b_logical_ram_depth = 1024, ram_block1a_23.port_b_logical_ram_width = 32, ram_block1a_23.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_23.power_up_uninitialized = "false", ram_block1a_23.ram_block_type = "M4K", ram_block1a_23.lpm_type = "cyclone_ram_block", ram_block1a_23.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_24 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[24]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_24portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_24.connectivity_checking = "OFF", ram_block1a_24.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_24.init_file_layout = "port_b", ram_block1a_24.logical_ram_name = "ALTSYNCRAM", ram_block1a_24.mem_init0 = 1024'h1AA36D42B668FFCE4F7380F3521E56E5272F58F05FCD49314D63768699CABE0DA3FB591263C7DD2CEC4DF4B8544596A75FAE2475BAF48C2F21713A90CFD665387462B9D891B6BBC22B14F14112C8AEA8CB56EB54C5648A73B18E06D925EB61CD27564EFC86965A21D8B30345FB7E2CCF834A351E0555AD30FFD46D18933EC8D8, ram_block1a_24.mixed_port_feed_through_mode = "old", ram_block1a_24.operation_mode = "dual_port", ram_block1a_24.port_a_address_clear = "none", ram_block1a_24.port_a_address_width = 10, ram_block1a_24.port_a_data_in_clear = "none", ram_block1a_24.port_a_data_width = 1, ram_block1a_24.port_a_first_address = 0, ram_block1a_24.port_a_first_bit_number = 24, ram_block1a_24.port_a_last_address = 1023, ram_block1a_24.port_a_logical_ram_depth = 1024, ram_block1a_24.port_a_logical_ram_width = 32, ram_block1a_24.port_a_write_enable_clear = "none", ram_block1a_24.port_b_address_clear = "none", ram_block1a_24.port_b_address_clock = "clock0", ram_block1a_24.port_b_address_width = 10, ram_block1a_24.port_b_data_out_clear = "none", ram_block1a_24.port_b_data_out_clock = "clock0", ram_block1a_24.port_b_data_width = 1, ram_block1a_24.port_b_first_address = 0, ram_block1a_24.port_b_first_bit_number = 24, ram_block1a_24.port_b_last_address = 1023, ram_block1a_24.port_b_logical_ram_depth = 1024, ram_block1a_24.port_b_logical_ram_width = 32, ram_block1a_24.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_24.power_up_uninitialized = "false", ram_block1a_24.ram_block_type = "M4K", ram_block1a_24.lpm_type = "cyclone_ram_block", ram_block1a_24.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_25 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[25]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_25portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_25.connectivity_checking = "OFF", ram_block1a_25.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_25.init_file_layout = "port_b", ram_block1a_25.logical_ram_name = "ALTSYNCRAM", ram_block1a_25.mem_init0 = 1024'hB508A1F0C9EC858FEEE2823930C7C2C769A02584E14542DFE2BE687B1EF1484F6377F4D0166A40921F6DA3921890E085D13B86C8104FBBA4DF2E5CCF54B38E6B8F9AC9F5499C04DBA2F6EA2F261DE9320A53456CDC102531D9824D7C74596A48431A2D9D29E844CAAB341AC6FCAE6C10123B51AF76C95A5F72AD3ACBB0E940CC, ram_block1a_25.mixed_port_feed_through_mode = "old", ram_block1a_25.operation_mode = "dual_port", ram_block1a_25.port_a_address_clear = "none", ram_block1a_25.port_a_address_width = 10, ram_block1a_25.port_a_data_in_clear = "none", ram_block1a_25.port_a_data_width = 1, ram_block1a_25.port_a_first_address = 0, ram_block1a_25.port_a_first_bit_number = 25, ram_block1a_25.port_a_last_address = 1023, ram_block1a_25.port_a_logical_ram_depth = 1024, ram_block1a_25.port_a_logical_ram_width = 32, ram_block1a_25.port_a_write_enable_clear = "none", ram_block1a_25.port_b_address_clear = "none", ram_block1a_25.port_b_address_clock = "clock0", ram_block1a_25.port_b_address_width = 10, ram_block1a_25.port_b_data_out_clear = "none", ram_block1a_25.port_b_data_out_clock = "clock0", ram_block1a_25.port_b_data_width = 1, ram_block1a_25.port_b_first_address = 0, ram_block1a_25.port_b_first_bit_number = 25, ram_block1a_25.port_b_last_address = 1023, ram_block1a_25.port_b_logical_ram_depth = 1024, ram_block1a_25.port_b_logical_ram_width = 32, ram_block1a_25.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_25.power_up_uninitialized = "false", ram_block1a_25.ram_block_type = "M4K", ram_block1a_25.lpm_type = "cyclone_ram_block", ram_block1a_25.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_26 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[26]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_26portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_26.connectivity_checking = "OFF", ram_block1a_26.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_26.init_file_layout = "port_b", ram_block1a_26.logical_ram_name = "ALTSYNCRAM", ram_block1a_26.mem_init0 = 1024'h98E061E9E4EC9E9FDFD5809C3D5928C8FE5B56808CA576FE8C39A5CD5BAF3BE0E4C848C9277E975C73BA172F845738A745C8A81DE12D50019C178D4663BEA695CF9441DA0B791C471DBE2FC1C8EAF9530B3AF4DA29ACCBAA5C6D3794F458C5A84406A0BF784EF22E9ED5657F9145AFEE77B384C83FA0EF9DC80C22540AEC98CB, ram_block1a_26.mixed_port_feed_through_mode = "old", ram_block1a_26.operation_mode = "dual_port", ram_block1a_26.port_a_address_clear = "none", ram_block1a_26.port_a_address_width = 10, ram_block1a_26.port_a_data_in_clear = "none", ram_block1a_26.port_a_data_width = 1, ram_block1a_26.port_a_first_address = 0, ram_block1a_26.port_a_first_bit_number = 26, ram_block1a_26.port_a_last_address = 1023, ram_block1a_26.port_a_logical_ram_depth = 1024, ram_block1a_26.port_a_logical_ram_width = 32, ram_block1a_26.port_a_write_enable_clear = "none", ram_block1a_26.port_b_address_clear = "none", ram_block1a_26.port_b_address_clock = "clock0", ram_block1a_26.port_b_address_width = 10, ram_block1a_26.port_b_data_out_clear = "none", ram_block1a_26.port_b_data_out_clock = "clock0", ram_block1a_26.port_b_data_width = 1, ram_block1a_26.port_b_first_address = 0, ram_block1a_26.port_b_first_bit_number = 26, ram_block1a_26.port_b_last_address = 1023, ram_block1a_26.port_b_logical_ram_depth = 1024, ram_block1a_26.port_b_logical_ram_width = 32, ram_block1a_26.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_26.power_up_uninitialized = "false", ram_block1a_26.ram_block_type = "M4K", ram_block1a_26.lpm_type = "cyclone_ram_block", ram_block1a_26.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_27 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[27]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_27portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_27.connectivity_checking = "OFF", ram_block1a_27.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_27.init_file_layout = "port_b", ram_block1a_27.logical_ram_name = "ALTSYNCRAM", ram_block1a_27.mem_init0 = 1024'h6763C0A526A1266DAFF7819AAE7965A16A8019BD5DA53B54541FD0DA036A03366FE06BD9C7FE5201383015C8F8838B09E08DBF9D8D1A1DAEFA7C45289637B454A36467AE0138C0819F67E6721C8001C346ABE4F447C8792F7746FFB5B9870E4F747CD1A133B03314763FD7DDB4C3634ED5AC8F1AA1BD5C081BDBCDAF8DD33F03, ram_block1a_27.mixed_port_feed_through_mode = "old", ram_block1a_27.operation_mode = "dual_port", ram_block1a_27.port_a_address_clear = "none", ram_block1a_27.port_a_address_width = 10, ram_block1a_27.port_a_data_in_clear = "none", ram_block1a_27.port_a_data_width = 1, ram_block1a_27.port_a_first_address = 0, ram_block1a_27.port_a_first_bit_number = 27, ram_block1a_27.port_a_last_address = 1023, ram_block1a_27.port_a_logical_ram_depth = 1024, ram_block1a_27.port_a_logical_ram_width = 32, ram_block1a_27.port_a_write_enable_clear = "none", ram_block1a_27.port_b_address_clear = "none", ram_block1a_27.port_b_address_clock = "clock0", ram_block1a_27.port_b_address_width = 10, ram_block1a_27.port_b_data_out_clear = "none", ram_block1a_27.port_b_data_out_clock = "clock0", ram_block1a_27.port_b_data_width = 1, ram_block1a_27.port_b_first_address = 0, ram_block1a_27.port_b_first_bit_number = 27, ram_block1a_27.port_b_last_address = 1023, ram_block1a_27.port_b_logical_ram_depth = 1024, ram_block1a_27.port_b_logical_ram_width = 32, ram_block1a_27.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_27.power_up_uninitialized = "false", ram_block1a_27.ram_block_type = "M4K", ram_block1a_27.lpm_type = "cyclone_ram_block", ram_block1a_27.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_28 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[28]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_28portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_28.connectivity_checking = "OFF", ram_block1a_28.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_28.init_file_layout = "port_b", ram_block1a_28.logical_ram_name = "ALTSYNCRAM", ram_block1a_28.mem_init0 = 1024'h11A835FEA7CD6278E71BA7BDAE5883BE4C95537164FED0D374E254FAC76329F38876635422F2491D57616B1FF32CCD36BB6507DCB9C758267C19407CA243CBF264E411080B3751051C05217B56C07CCBDD2FEF13D926D66EF5B0E561C008F3F12509AD0D897448CD09194C908A6F042EA69885C1DDA9F297419E8E074799A12D, ram_block1a_28.mixed_port_feed_through_mode = "old", ram_block1a_28.operation_mode = "dual_port", ram_block1a_28.port_a_address_clear = "none", ram_block1a_28.port_a_address_width = 10, ram_block1a_28.port_a_data_in_clear = "none", ram_block1a_28.port_a_data_width = 1, ram_block1a_28.port_a_first_address = 0, ram_block1a_28.port_a_first_bit_number = 28, ram_block1a_28.port_a_last_address = 1023, ram_block1a_28.port_a_logical_ram_depth = 1024, ram_block1a_28.port_a_logical_ram_width = 32, ram_block1a_28.port_a_write_enable_clear = "none", ram_block1a_28.port_b_address_clear = "none", ram_block1a_28.port_b_address_clock = "clock0", ram_block1a_28.port_b_address_width = 10, ram_block1a_28.port_b_data_out_clear = "none", ram_block1a_28.port_b_data_out_clock = "clock0", ram_block1a_28.port_b_data_width = 1, ram_block1a_28.port_b_first_address = 0, ram_block1a_28.port_b_first_bit_number = 28, ram_block1a_28.port_b_last_address = 1023, ram_block1a_28.port_b_logical_ram_depth = 1024, ram_block1a_28.port_b_logical_ram_width = 32, ram_block1a_28.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_28.power_up_uninitialized = "false", ram_block1a_28.ram_block_type = "M4K", ram_block1a_28.lpm_type = "cyclone_ram_block", ram_block1a_28.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_29 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[29]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_29portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_29.connectivity_checking = "OFF", ram_block1a_29.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_29.init_file_layout = "port_b", ram_block1a_29.logical_ram_name = "ALTSYNCRAM", ram_block1a_29.mem_init0 = 1024'h25F8419EB27E4AF71673C912D18C3E4813C49ACE00FE4D577C357B606A8E0257A3EFF4665577F294E8E039BE6E2DDF5F1778445ADC8B793ACA069B27751D88938F67D700A549A04C9BBE9EB4764F3639990E37D0CD4E31D0757016300E64569689B9F2D69D305B2BDA77C9D01922E83BE2368E2E08C09731CCEF6BF4771BD045, ram_block1a_29.mixed_port_feed_through_mode = "old", ram_block1a_29.operation_mode = "dual_port", ram_block1a_29.port_a_address_clear = "none", ram_block1a_29.port_a_address_width = 10, ram_block1a_29.port_a_data_in_clear = "none", ram_block1a_29.port_a_data_width = 1, ram_block1a_29.port_a_first_address = 0, ram_block1a_29.port_a_first_bit_number = 29, ram_block1a_29.port_a_last_address = 1023, ram_block1a_29.port_a_logical_ram_depth = 1024, ram_block1a_29.port_a_logical_ram_width = 32, ram_block1a_29.port_a_write_enable_clear = "none", ram_block1a_29.port_b_address_clear = "none", ram_block1a_29.port_b_address_clock = "clock0", ram_block1a_29.port_b_address_width = 10, ram_block1a_29.port_b_data_out_clear = "none", ram_block1a_29.port_b_data_out_clock = "clock0", ram_block1a_29.port_b_data_width = 1, ram_block1a_29.port_b_first_address = 0, ram_block1a_29.port_b_first_bit_number = 29, ram_block1a_29.port_b_last_address = 1023, ram_block1a_29.port_b_logical_ram_depth = 1024, ram_block1a_29.port_b_logical_ram_width = 32, ram_block1a_29.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_29.power_up_uninitialized = "false", ram_block1a_29.ram_block_type = "M4K", ram_block1a_29.lpm_type = "cyclone_ram_block", ram_block1a_29.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_30 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[30]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_30portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_30.connectivity_checking = "OFF", ram_block1a_30.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_30.init_file_layout = "port_b", ram_block1a_30.logical_ram_name = "ALTSYNCRAM", ram_block1a_30.mem_init0 = 1024'h0944A561E78231B263F0D21EC8FD8B58FC2CCCCC152785EC1A5672B79A31FA82717BCEB7A411511F907747B825806010E7ADBA694A1268101FBCFD2DE97C35CB7FDB0464C2FA8092F85928963C318C92752194DF2E67D8302F40FED40FDAF8ACF222D29C70F9BCEA09B396C331BCA21B3FF1B0A1CD66305377AE95066DB9B6B5, ram_block1a_30.mixed_port_feed_through_mode = "old", ram_block1a_30.operation_mode = "dual_port", ram_block1a_30.port_a_address_clear = "none", ram_block1a_30.port_a_address_width = 10, ram_block1a_30.port_a_data_in_clear = "none", ram_block1a_30.port_a_data_width = 1, ram_block1a_30.port_a_first_address = 0, ram_block1a_30.port_a_first_bit_number = 30, ram_block1a_30.port_a_last_address = 1023, ram_block1a_30.port_a_logical_ram_depth = 1024, ram_block1a_30.port_a_logical_ram_width = 32, ram_block1a_30.port_a_write_enable_clear = "none", ram_block1a_30.port_b_address_clear = "none", ram_block1a_30.port_b_address_clock = "clock0", ram_block1a_30.port_b_address_width = 10, ram_block1a_30.port_b_data_out_clear = "none", ram_block1a_30.port_b_data_out_clock = "clock0", ram_block1a_30.port_b_data_width = 1, ram_block1a_30.port_b_first_address = 0, ram_block1a_30.port_b_first_bit_number = 30, ram_block1a_30.port_b_last_address = 1023, ram_block1a_30.port_b_logical_ram_depth = 1024, ram_block1a_30.port_b_logical_ram_width = 32, ram_block1a_30.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_30.power_up_uninitialized = "false", ram_block1a_30.ram_block_type = "M4K", ram_block1a_30.lpm_type = "cyclone_ram_block", ram_block1a_30.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; cyclone_ram_block ram_block1a_31 ( .clk0(clock0), .portaaddr({address_a_wire[9:0]}), .portadatain({data_a[31]}), .portadataout(), .portawe(wren_a), .portbaddr({address_b_wire[9:0]}), .portbdataout(wire_ram_block1a_31portbdataout[0:0]), .portbrewe(1'b1) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena0(1'b1), .ena1(1'b1), .portabyteenamasks({1{1'b1}}), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_31.connectivity_checking = "OFF", ram_block1a_31.init_file = "./MersenneTwister/MT_RAM_init.mif", ram_block1a_31.init_file_layout = "port_b", ram_block1a_31.logical_ram_name = "ALTSYNCRAM", ram_block1a_31.mem_init0 = 1024'h7F1198925723920B9FEB7D28D66EE11FEA77269C61A18609A5CCCC28FAB7B45D7779278F97CA66C825F0CEE6B841DD7B97DEB4951080E8B4A7FC6B5F8209AF6D07E5F9F195B8E660A9DE73A006E38783C80EE5CA64DE2006956683F8D3D89805CE2504CFC6E4FF000AB148BA622AE5C539BB6AEF9A0C357B7E5ABEDE60FFBA31, ram_block1a_31.mixed_port_feed_through_mode = "old", ram_block1a_31.operation_mode = "dual_port", ram_block1a_31.port_a_address_clear = "none", ram_block1a_31.port_a_address_width = 10, ram_block1a_31.port_a_data_in_clear = "none", ram_block1a_31.port_a_data_width = 1, ram_block1a_31.port_a_first_address = 0, ram_block1a_31.port_a_first_bit_number = 31, ram_block1a_31.port_a_last_address = 1023, ram_block1a_31.port_a_logical_ram_depth = 1024, ram_block1a_31.port_a_logical_ram_width = 32, ram_block1a_31.port_a_write_enable_clear = "none", ram_block1a_31.port_b_address_clear = "none", ram_block1a_31.port_b_address_clock = "clock0", ram_block1a_31.port_b_address_width = 10, ram_block1a_31.port_b_data_out_clear = "none", ram_block1a_31.port_b_data_out_clock = "clock0", ram_block1a_31.port_b_data_width = 1, ram_block1a_31.port_b_first_address = 0, ram_block1a_31.port_b_first_bit_number = 31, ram_block1a_31.port_b_last_address = 1023, ram_block1a_31.port_b_logical_ram_depth = 1024, ram_block1a_31.port_b_logical_ram_width = 32, ram_block1a_31.port_b_read_enable_write_enable_clock = "clock0", ram_block1a_31.power_up_uninitialized = "false", ram_block1a_31.ram_block_type = "M4K", ram_block1a_31.lpm_type = "cyclone_ram_block", ram_block1a_31.lpm_hint = "DONT_POWER_OPTIMIZE=ON"; assign address_a_wire = address_a, address_b_wire = address_b, q_b = {wire_ram_block1a_31portbdataout[0], wire_ram_block1a_30portbdataout[0], wire_ram_block1a_29portbdataout[0], wire_ram_block1a_28portbdataout[0], wire_ram_block1a_27portbdataout[0], wire_ram_block1a_26portbdataout[0], wire_ram_block1a_25portbdataout[0], wire_ram_block1a_24portbdataout[0], wire_ram_block1a_23portbdataout[0], wire_ram_block1a_22portbdataout[0], wire_ram_block1a_21portbdataout[0], wire_ram_block1a_20portbdataout[0], wire_ram_block1a_19portbdataout[0], wire_ram_block1a_18portbdataout[0], wire_ram_block1a_17portbdataout[0], wire_ram_block1a_16portbdataout[0], wire_ram_block1a_15portbdataout[0], wire_ram_block1a_14portbdataout[0], wire_ram_block1a_13portbdataout[0], wire_ram_block1a_12portbdataout[0], wire_ram_block1a_11portbdataout[0], wire_ram_block1a_10portbdataout[0], wire_ram_block1a_9portbdataout[0], wire_ram_block1a_8portbdataout[0], wire_ram_block1a_7portbdataout[0], wire_ram_block1a_6portbdataout[0], wire_ram_block1a_5portbdataout[0], wire_ram_block1a_4portbdataout[0], wire_ram_block1a_3portbdataout[0], wire_ram_block1a_2portbdataout[0], wire_ram_block1a_1portbdataout[0], wire_ram_block1a_0portbdataout[0]}; endmodule //RAM_2port_1024x32_altsyncram //VALID FILE // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module RAM_2port_1024x32 ( clock, data, rdaddress, wraddress, wren, q)/* synthesis synthesis_clearbox = 1 */; input clock; input [31:0] data; input [9:0] rdaddress; input [9:0] wraddress; input wren; output [31:0] q; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 clock; tri0 wren; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire [31:0] sub_wire0; wire [31:0] q = sub_wire0[31:0]; RAM_2port_1024x32_altsyncram RAM_2port_1024x32_altsyncram_component ( .address_a (wraddress), .clock0 (clock), .data_a (data), .wren_a (wren), .address_b (rdaddress), .q_b (sub_wire0)); endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" // Retrieval info: PRIVATE: CLRdata NUMERIC "0" // Retrieval info: PRIVATE: CLRq NUMERIC "0" // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" // Retrieval info: PRIVATE: CLRrren NUMERIC "0" // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" // Retrieval info: PRIVATE: CLRwren NUMERIC "0" // Retrieval info: PRIVATE: Clock NUMERIC "0" // Retrieval info: PRIVATE: Clock_A NUMERIC "0" // Retrieval info: PRIVATE: Clock_B NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768" // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "./MersenneTwister/MT_RAM_init.mif" // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" // Retrieval info: PRIVATE: REGdata NUMERIC "1" // Retrieval info: PRIVATE: REGq NUMERIC "0" // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" // Retrieval info: PRIVATE: REGrren NUMERIC "1" // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" // Retrieval info: PRIVATE: REGwren NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1" // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" // Retrieval info: PRIVATE: VarWidth NUMERIC "0" // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: enable NUMERIC "0" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" // Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: INIT_FILE STRING "./MersenneTwister/MT_RAM_init.mif" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024" // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K" // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" // Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]" // Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" // Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0 // Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0 // Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2port_1024x32.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2port_1024x32.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2port_1024x32.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2port_1024x32.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2port_1024x32_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2port_1024x32_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2port_1024x32_syn.v TRUE // Retrieval info: LIB_FILE: altera_mf