module MersenneTwister(
	input clk,
	output reg [31:0] rnd);

	parameter N = 10'd624;
	parameter M = 10'd397;

	reg [31:0] y_1, y_2, y_3, y_4, y_5;

	reg ram_wren;
	reg [9:0] ram_wadd;
	reg [31:0] ram_wdata;

	reg [9:0] ram1_radd;
	wire [31:0] ram1_rdata;
	RAM_2port_1024x32 ram1(
		.clock(clk),
		.data(ram_wdata),
		.rdaddress(ram1_radd),
		.wraddress(ram_wadd),
		.wren(ram_wren),
		.q(ram1_rdata));

	reg [9:0] ram2_radd;
	wire [31:0] ram2_rdata;
	RAM_2port_1024x32 ram2(
		.clock(clk),
		.data(ram_wdata),
		.rdaddress(ram2_radd),
		.wraddress(ram_wadd),
		.wren(ram_wren),
		.q(ram2_rdata));

	reg [9:0] ram3_radd;
	wire [31:0] ram3_rdata;
	RAM_2port_1024x32 ram3(
		.clock(clk),
		.data(ram_wdata),
		.rdaddress(ram3_radd),
		.wraddress(ram_wadd),
		.wren(ram_wren),
		.q(ram3_rdata));


	initial
	begin
		rnd <= 0;
		y_1 <= 0;
		y_2 <= 0;
		y_3 <= 0;
		y_4 <= 0;
		y_5 <= 0;

		ram_wren <= 0;
		ram_wadd <= 0;
		ram_wdata <= 0;

		ram1_radd <= 0;
		ram2_radd <= 1'b1;
		ram3_radd <= M;
	end

	always @(posedge clk)
	begin
		if (ram2_rdata[0] == 0)
			ram_wdata <= ram3_rdata ^ {1'b0,ram1_rdata[31],ram2_rdata[30:1]};
		else
			ram_wdata <= ram3_rdata ^ {1'b0,ram1_rdata[31],ram2_rdata[30:1]} ^ 32'h9908b0df;

		y_1 <= ram1_rdata;
		y_2 <= y_1 ^ (y_1 >> 11);
		y_3 <= y_2 ^ ((y_2 << 7) & 32'h9d2c5680);
		y_4 <= y_3 ^ ((y_3 << 15) & 32'hefc60000);
		y_5 <= y_4 ^ (y_4 >> 18);
			
//		$display("%d",y);	
		rnd <= y_5;

		if (ram2_radd == (N-1)) ram2_radd <= 0;
		else ram2_radd <= ram2_radd + 1'b1;

		if (ram2_radd + M >= N) ram3_radd <= ram2_radd + M - N;
		else ram3_radd <= ram2_radd + M;


		ram1_radd <= ram2_radd;
		ram_wadd <= ram2_radd;
		ram_wren <= 1'b1;
//		$display("%d, %d, %d", ram1_radd, ram2_radd, ram3_radd);
	end
endmodule