module LTU_T( /* Front panel: */ // CTP Connector /*input*/output CON_SPARE1, // CTP_ORBIT, /*input*/output CON_SPARE2, // CTP_PREPULSE, /*input*/output CON_SPARE3, // CTP_L0, /*input*/output CON_SPARE4, // CTP_L1, (* useioff = 1 *) input TTC_B, // CTP_L1Data, (* useioff = 1 *) input TTC_A, // CTP_L2STROBE, input LM_GL, // CTP_L2DATA, // Double coaxial connectors output OUT_A, (* useioff = 1 *) output OUT_B, (* useioff = 1 *) input IN_PULSER, (* useioff = 1 *) output reg OUT_L1, /*input*/output IN_SPARE, // IN or OUT (* useioff = 1 *) output reg OUT_SPARE, // (* useioff = 1 *) output reg OUT_ORBIT, input IN_BC, (* useioff = 1 *) output reg OUT_PREPULSE, // Lemo PCB connectors output OUT_1L0, output OUT_2L0, output OUT_3L0, // OUT_3L0 or IN_LVDS /*input*/ output IN_LVDS, // (* useioff = 1 *) output reg OUT_BUSY, (* useioff = 1 *) input IN_BUSY1, /*input*/output IN_BUSY2, // LEDs output LED_RD, output LED_WR, output LED_A, output LED_B, output LED_PLSR, output LED_L1, output LED_SPARE, output LED_ORBIT, output LED_BC, output LED_PP, output LED_BUSY, output LED_L0, /* Clock */ input DL_BC, (* useioff = 1 *) output [4:0] BC_DELAY, output LED_LOCK, /* Test PINs */ output TEST_C1, output TEST_C2, output TEST_C3, output TEST_C4, output TEST_C5, output TEST_C6, output TEST_C7, output TEST_C8, /* Logic Analyzer */ output LA_CLOCK, output LA_A2_0, output LA_A2_1, output LA_A2_2, output LA_A2_3, output LA_A2_4, output LA_A2_5, output LA_A2_6, output LA_A2_7, output LA_A3_0, output LA_A3_1, output LA_A3_2, output LA_A3_3, output LA_A3_4, output LA_A3_5, output LA_A3_6, output LA_A3_7, output LA_C3_4, output LA_C3_5, output LA_C3_6, output LA_C3_7, /* SNAP-SHOT MEMORY */ output SSM_CLK, (* useioff = 1 *) output [19:0] SSM_A, output SSM_CE, (* useioff = 1 *) output SSM_WRITE, (* useioff = 1 *) inout [17:0] SSM_DQ, /* FPGA configuring */ (* useioff = 1 *) output reg INIT_DONE, /* ADC */ output ADC_IN, output ADC_CS, output ADC_CLK, inout ADC_SDATA, /* VME J2 */ output BP_L1, output BP_ORBIT, output OBP_BC, output BP_L1_DATA, output BP_L2_STROBE, output BP_L0, output BP_PREPULSE, output BP_L2_DATA, (* useioff = 1 *) inout [31:0] D, /* VME FPGA */ (* useioff = 1 *) input [9:0] ADD, output SPARE_1, output SPARE_2, output SPARE_3, output SPARE_4, (* useioff = 1 *) input WRITE, (* useioff = 1 *) input MRESET, output DWB, (* useioff = 1 *) input STROBE, /*input*/output MSTROBE, /*input*/output VME_CLK ); reg MRESET_sync; reg BUSY_GTU; //************************************************ // PLL //************************************************ reg [1:0] reset_after_pll_locked_wait; reg pll_reset; reg reset_after_pll_locked; reg pll_locked_save; wire pll_locked; wire clk; // clock from PLL wire clk_180; // clock from PLL //************************************************ // CTP Emulator //************************************************ reg PULSER_sync; wire CTPEmu_enable; wire CTPEmu_start; wire [1:0] CTPEmu_mode; wire [5:0] LMtoLMSA; wire [25:0] CTPEmu_freq; wire [31:0] CTPEmu_threshold; wire [31:0] CTPEmu_LMSA_threshold; wire CTPEmu_LM; wire CTPEmu_LMSA; wire [31:0] CTPEmu_rnd; wire [8:0] CTPEmu_state_mon; //************************************************ // Protocol Converter //************************************************ reg LM_GL_sync; wire LM_GL_inv; wire LM_to_pc; reg TTC_A_sync; reg BUSY_GTU_sync; wire [5:0] LMtoL0ll; wire [5:0] LMtoL0ul; wire [5:0] LMtoL0delay; wire [6:0] LMtoL0rec; wire [8:0] LMtoL1ll; wire [8:0] LMtoL1ul; wire [8:0] LMtoL1delay; wire [8:0] LMtoL1rec; wire [10:0] LMtoL1acc; wire LM; wire L0; wire L1; wire PC_BUSY; wire [31:0] PC_counter_ErrorState; wire [7:0] PC_state_mon; //*********************************************** // LED Controler //************************************************ wire LEDs_test; assign LED_LOCK = pll_locked; //************************************************ // PT commands //************************************************ wire ptcom_busy; wire ptcom_seq; wire ptcom_reset; wire ptcom_mux; wire ptcom_en; wire [2:0] ptcom_code; //************************************************ // TTC-B parser //************************************************ reg TTC_B_sync; wire [11:0] BCID; wire [23:0] OrbitID; //************************************************ // SSM Controler //************************************************ wire SSM_start; wire SSM_stop; wire SSM_loop; wire SSM_read; wire [2:0] SSM_mode; wire [17:0] SSM_data; wire SSM_busy; //************************************************ // Switch Oscilloscope Outputs //************************************************ wire [3:0] switchA; wire [3:0] switchB; //************************************************ // Counter //************************************************ wire reset_counter; reg TTC_A_cnt; reg TTC_A_save; reg LM_GL_cnt; reg LM_GL_save; reg BUSY_cnt; reg BUSY_save; wire [31:0] counter_Clock; wire [31:0] counter_TTC_A; wire [31:0] counter_LM_GL; wire [31:0] counter_BUSY; wire [31:0] counter_LM; wire [31:0] counter_L0; wire [31:0] counter_L1; wire [31:0] counter_L0_e_1; wire [31:0] counter_L0_e_2; wire [31:0] counter_L0_e_3; wire [31:0] counter_L0_e_4; wire [31:0] counter_L0_e_m; wire [31:0] counter_L0_l_1; wire [31:0] counter_L0_l_2; wire [31:0] counter_L0_l_3; wire [31:0] counter_L0_l_4; wire [31:0] counter_L0_l_m; wire [31:0] counter_L1_e_1; wire [31:0] counter_L1_e_2; wire [31:0] counter_L1_e_3; wire [31:0] counter_L1_e_4; wire [31:0] counter_L1_e_m; wire [31:0] counter_L1_l_1; wire [31:0] counter_L1_l_2; wire [31:0] counter_L1_l_3; wire [31:0] counter_L1_l_4; wire [31:0] counter_L1_l_m; //************************************************ // Communicator //************************************************ wire L0L1_disable; wire BUSY_disable; wire LM_inp_disable; wire A_dis; wire [1:0] B_dis; //************************************************ // PLL //************************************************ PLL pll( .areset(pll_reset), .inclk0(DL_BC), .c0(clk), .c1(clk_180), .locked(pll_locked)); //************************************************ // CTP Emulator //************************************************ CTPEmulator emu( .clk(clk), .reset(MRESET_sync), .enable(CTPEmu_enable), .pulser(PULSER_sync), .start_single(CTPEmu_start), .mode(CTPEmu_mode), .BUSY_GTU(BUSY_GTU_sync), .BUSY_int(PC_BUSY), .LMtoLMSA(LMtoLMSA), .CTPEmu_freq(CTPEmu_freq), .CTPEmu_threshold(CTPEmu_threshold), .CTPEmu_LMSA_threshold(CTPEmu_LMSA_threshold), .LM(CTPEmu_LM), .LM_SA(CTPEmu_LMSA), .rnd(CTPEmu_rnd), .state_mon(CTPEmu_state_mon)); //************************************************ // Protocol Converter //************************************************ assign LM_to_pc = CTPEmu_enable ? CTPEmu_LM : (LM_inp_disable ? 1'b0 : (LM_GL_inv ? (!LM_GL_sync) : LM_GL_sync)); ProtocolConverter pc( .clk(clk), .reset(reset_after_pll_locked || MRESET_sync || ptcom_reset), .reset_counter(reset_counter), .LM_GL(LM_to_pc), .TTC_A(TTC_A_sync), .BUSY_GTU(BUSY_GTU_sync), .LMtoL0ll(LMtoL0ll), .LMtoL0ul(LMtoL0ul), .LMtoL0delay(LMtoL0delay), .LMtoL0rec(LMtoL0rec), .LMtoL1ll(LMtoL1ll), .LMtoL1ul(LMtoL1ul), .LMtoL1delay(LMtoL1delay), .LMtoL1rec(LMtoL1rec), .LMtoL1acc(LMtoL1acc), .busy(PC_BUSY), .LM(LM), .L0(L0), .L1(L1), .counter_ErrorState(PC_counter_ErrorState), .counter_L0_e_1(counter_L0_e_1), .counter_L0_e_2(counter_L0_e_2), .counter_L0_e_3(counter_L0_e_3), .counter_L0_e_4(counter_L0_e_4), .counter_L0_e_m(counter_L0_e_m), .counter_L0_l_1(counter_L0_l_1), .counter_L0_l_2(counter_L0_l_2), .counter_L0_l_3(counter_L0_l_3), .counter_L0_l_4(counter_L0_l_4), .counter_L0_l_m(counter_L0_l_m), .counter_L1_e_1(counter_L1_e_1), .counter_L1_e_2(counter_L1_e_2), .counter_L1_e_3(counter_L1_e_3), .counter_L1_e_4(counter_L1_e_4), .counter_L1_e_m(counter_L1_e_m), .counter_L1_l_1(counter_L1_l_1), .counter_L1_l_2(counter_L1_l_2), .counter_L1_l_3(counter_L1_l_3), .counter_L1_l_4(counter_L1_l_4), .counter_L1_l_m(counter_L1_l_m), .state_mon(PC_state_mon)); //*********************************************** // LED Controler //************************************************ LED_control_RDWR rdwr( .clk(clk), .STROBE(STROBE), .WRITE(WRITE), .LED_RD(LED_RD), .LED_WR(LED_WR)); LED_control LEDs( .clk(clk), .reset(reset_after_pll_locked || MRESET_sync), .test(LEDs_test), .on({ OUT_A, // 1 OUT_B, // 2 IN_PULSER, // 3 OUT_L1, // 4 //TTCtrd_A OUT_SPARE, // 5 //LM_SA OUT_ORBIT, // 6 //TTCtrd_B !DL_BC, // 7 //BC, OUT_PREPULSE, // 8 BUSY_GTU_sync, // 9 L0}), // 10 .LEDs({ LED_A, // 1 LED_B, // 2 LED_PLSR, // 3 LED_L1, // 4 LED_SPARE, // 5 LED_ORBIT, // 6 LED_BC, // 7 LED_PP, // 8 LED_BUSY, // 9 LED_L0})); // 10 //************************************************ // PT commands //************************************************ PTcommands pt( .clk(clk), .enable(ptcom_en), .code(ptcom_code), .PTsequence(ptcom_seq), .reset(ptcom_reset), .PTsending(ptcom_busy)); //************************************************ // TTC-B parser //************************************************ TTCB_parser parser( .clk(clk), .reset(MRESET_sync), .TTC_B(TTC_B_sync), .BCID(BCID), .OrbitID(OrbitID)); //************************************************ // SSM Controler //************************************************ SSMcontroler ssm( .clk(clk), .clk_180(clk_180), .reset(MRESET_sync), .SSM_start(SSM_start), .SSM_stop(SSM_stop), .SSM_loop(SSM_loop), .SSM_read(SSM_read), .SSM_mode(SSM_mode), .counter_Clock(counter_Clock), .PC_state_mon(PC_state_mon), .CTPEmu_state_mon(CTPEmu_state_mon), .rnd(CTPEmu_rnd), .inp_LM(LM_GL), .inp_TTC_A(TTC_A), .inp_TTC_B(TTC_B), .inp_PLSR(IN_PULSER), .inp_BUSY(IN_BUSY1), .outp_L1(OUT_L1), .outp_SPARE(CTPEmu_LMSA), .outp_ORBIT(OUT_ORBIT), .outp_BUSY(BUSY_GTU), .CTPEmu_LM(CTPEmu_LM), .LM_GL_sync(LM_GL_sync), .TTC_A_sync(TTC_A_sync), .TTCtrd_A(LM || L0 || L1), .BCID(BCID), .OrbitID(OrbitID), .SSM_CE(SSM_CE), .SSM_CLK(SSM_CLK), .SSM_WRITE(SSM_WRITE), .SSM_A(SSM_A), .SSM_data(SSM_data), .SSM_busy(SSM_busy), .SSM_DQ(SSM_DQ)); //************************************************ // Switch Oscilloscope Outputs //************************************************ mux_Async A( .reset(MRESET_sync), .sw(switchA), .in01(IN_BC), .in02(DL_BC), .in03(clk), .in04(LM_GL), .in05(TTC_A), .in06(TTC_B), .in07(IN_PULSER), .in08(IN_BUSY1), .in09(WRITE), .in10(STROBE), .in11(MRESET), .in12(ADD[0]), .in13(D[0]), .in14(SSM_DQ[0]), .in15(1'b0), .out(OUT_A)); mux_sync sB( .clk(clk), .reset(MRESET_sync), .sw(switchB), .in01(LM_GL), .in02(TTC_A), //TTC_A_sync .in03(TTC_B), //TTC_B_sync .in04(BUSY_GTU), //OUT_BUSY .in05(CTPEmu_LMSA), //OUT_SPARE .in06(OUT_ORBIT), //delayed by 1 cc .in07(LM || L0 || L1), //Trigger-Sequence .in08(WRITE), //WRITE_sync .in09(SSM_DQ[0]), //SSM_DATA_sync[0] .in10(LM || L0 || L1 || CTPEmu_LMSA), .in11(CTPEmu_LM), .in12(1'b0), .in13(1'b0), .in14(1'b0), .in15(1'b0), .out(OUT_B)); //************************************************ // Counter //************************************************ counter_BC BC_counter( .clock(clk), .sclr(reset_counter), .q(counter_Clock)); counter_32bit_up TTC_A_counter( .clock(clk), .cnt_en(TTC_A_cnt), .sclr(reset_counter), .q(counter_TTC_A)); counter_32bit_up LM_GL_counter( .clock(clk), .cnt_en(LM_GL_cnt), .sclr(reset_counter), .q(counter_LM_GL)); counter_32bit_up BUSY_counter( .clock(clk), .cnt_en(BUSY_cnt), .sclr(reset_counter), .q(counter_BUSY)); counter_32bit_up LM_counter( .clock(clk), .cnt_en(LM), .sclr(reset_counter), .q(counter_LM)); counter_32bit_up L0_counter( .clock(clk), .cnt_en(L0), .sclr(reset_counter), .q(counter_L0)); counter_32bit_up L1_counter( .clock(clk), .cnt_en(L1), .sclr(reset_counter), .q(counter_L1)); //************************************************ // Communicator //************************************************ Com Comm( .clk(clk), .reset(MRESET_sync), .counter_Clock(counter_Clock), .counter_LM(counter_LM), .counter_L0(counter_L0), .counter_L1(counter_L1), .counter_TTC_A(counter_TTC_A), .counter_LM_GL(counter_LM_GL), .counter_BUSY(counter_BUSY), .counter_ErrorState(PC_counter_ErrorState), .counter_L0_e_1(counter_L0_e_1), .counter_L0_e_2(counter_L0_e_2), .counter_L0_e_3(counter_L0_e_3), .counter_L0_e_4(counter_L0_e_4), .counter_L0_e_m(counter_L0_e_m), .counter_L0_l_1(counter_L0_l_1), .counter_L0_l_2(counter_L0_l_2), .counter_L0_l_3(counter_L0_l_3), .counter_L0_l_4(counter_L0_l_4), .counter_L0_l_m(counter_L0_l_m), .counter_L1_e_1(counter_L1_e_1), .counter_L1_e_2(counter_L1_e_2), .counter_L1_e_3(counter_L1_e_3), .counter_L1_e_4(counter_L1_e_4), .counter_L1_e_m(counter_L1_e_m), .counter_L1_l_1(counter_L1_l_1), .counter_L1_l_2(counter_L1_l_2), .counter_L1_l_3(counter_L1_l_3), .counter_L1_l_4(counter_L1_l_4), .counter_L1_l_m(counter_L1_l_m), .ptcom_busy(ptcom_busy), .BCID(BCID), .OrbitID(OrbitID), .SSM_busy(SSM_busy), .BUSY_GTU(BUSY_GTU), .PC_ErrorState(PC_state_mon[7:4]), .rnd(CTPEmu_rnd), .SSM_data(SSM_data), .ADDRESS(ADD), .STROBE(STROBE), .WRITE(WRITE), .reset_counter(reset_counter), .LEDs_test(LEDs_test), .L0L1_dis(L0L1_disable), .BUSY_dis(BUSY_disable), .LM_dis(LM_inp_disable), .LM_GL_inv(LM_GL_inv), .LMtoLMSA(LMtoLMSA), .LMtoL0ll(LMtoL0ll), .LMtoL0ul(LMtoL0ul), .LMtoL0delay(LMtoL0delay), .LMtoL0rec(LMtoL0rec), .LMtoL1ll(LMtoL1ll), .LMtoL1ul(LMtoL1ul), .LMtoL1delay(LMtoL1delay), .LMtoL1rec(LMtoL1rec), .LMtoL1acc(LMtoL1acc), .CTPEmu_enable(CTPEmu_enable), .CTPEmu_mode(CTPEmu_mode), .CTPEmu_start(CTPEmu_start), .CTPEmu_freq(CTPEmu_freq), .CTPEmu_threshold(CTPEmu_threshold), .CTPEmu_LMSA_threshold(CTPEmu_LMSA_threshold), .switchA(switchA), .switchB(switchB), .ptcom_en(ptcom_en), .ptcom_mux(ptcom_mux), .ptcom_code(ptcom_code), .A_dis(A_dis), .B_dis(B_dis), .SSM_mode(SSM_mode), .SSM_read(SSM_read), .SSM_start(SSM_start), .SSM_stop(SSM_stop), .SSM_loop(SSM_loop), .BC_delay(BC_DELAY), .Data(D)); //************************************************ // Initialisation of all registers //************************************************ initial begin // Outputs OUT_L1 <= 1'b0; OUT_ORBIT <= 1'b0; OUT_BUSY <= 1'b1; INIT_DONE <= 1'b0; OUT_SPARE <= 1'b0; // Internal registers MRESET_sync <= 1'b0; BUSY_GTU <= 1'b1; reset_after_pll_locked <= 0; reset_after_pll_locked_wait <= 0; pll_reset <= 0; pll_locked_save <= 0; LM_GL_sync <= 1'b0; TTC_A_sync <= 1'b0; BUSY_GTU_sync <= 1'b1; PULSER_sync <= 1'b0; TTC_B_sync <= 1'b0; TTC_A_cnt <= 1'b0; TTC_A_save <= 1'b0; LM_GL_cnt <= 1'b0; LM_GL_save <= 1'b0; BUSY_cnt <= 1'b0; BUSY_save <= 1'b0; end //************************************************ // Handling of // - PLL // - Input-/Outputsynchronization // - Edge detection for counters //************************************************ always @(posedge clk) begin if (MRESET_sync == 1'b1) begin MRESET_sync <= MRESET; // Outputs INIT_DONE <= 1'b0; // Internal registers reset_after_pll_locked <= 0; reset_after_pll_locked_wait <= 0; pll_reset <= 0; pll_locked_save <= 0; BUSY_GTU_sync <= 1'b1; TTC_A_cnt <= 1'b0; TTC_A_save <= 1'b0; LM_GL_cnt <= 1'b0; LM_GL_save <= 1'b0; BUSY_cnt <= 1'b0; BUSY_save <= 1'b0; end else begin // PLL pll_locked_save <= pll_locked; if (reset_after_pll_locked_wait == 2'b00) reset_after_pll_locked <= 0; else reset_after_pll_locked_wait <= reset_after_pll_locked_wait - 1'b1; if (pll_locked_save < pll_locked) begin reset_after_pll_locked <= 1; reset_after_pll_locked_wait <= 2'b11; end if (pll_locked == 1) INIT_DONE <= 1; // Inputs MRESET_sync <= MRESET; LM_GL_sync <= LM_GL; TTC_A_sync <= TTC_A; TTC_B_sync <= TTC_B; PULSER_sync <= IN_PULSER; BUSY_GTU_sync <= !BUSY_disable & BUSY_GTU; BUSY_GTU <= IN_BUSY1; // Edge detection for counter LM_GL_save <= LM_GL_sync; LM_GL_cnt <= LM_GL_sync & !LM_GL_save; TTC_A_save <= TTC_A_sync; TTC_A_cnt <= TTC_A_sync & !TTC_A_save; BUSY_save <= BUSY_GTU; BUSY_cnt <= BUSY_GTU & !BUSY_save; end end always @(posedge clk) begin if (MRESET_sync == 1'b1) begin // Outputs OUT_L1 <= 1'b0; OUT_ORBIT <= 1'b0; OUT_BUSY <= 1'b1; OUT_SPARE <= 1'b0; OUT_PREPULSE <= 1'b0; end else begin // Outputs if (B_dis[1] == 1'b1) OUT_ORBIT <= B_dis[0]; else OUT_ORBIT <= TTC_B; OUT_BUSY <= BUSY_GTU; OUT_SPARE <= CTPEmu_LMSA; if (A_dis == 1'b1) OUT_L1 <= 1'b0; else begin if (ptcom_mux == 1'b1) OUT_L1 <= ptcom_seq; else begin if (L0L1_disable == 1'b1) OUT_L1 <= LM; else OUT_L1 <= LM || L0 || L1; end end OUT_PREPULSE <= LM; end end assign TEST_C1 = 1'b0; assign TEST_C2 = 1'b0; assign TEST_C3 = 1'b0; assign TEST_C4 = 1'b0; assign TEST_C5 = 1'b0; assign TEST_C6 = 1'b0; assign TEST_C7 = 1'b0; assign TEST_C8 = 1'b0; assign OUT_1L0 = 1'b0; assign OUT_2L0 = 1'b0; assign OUT_3L0 = 1'b0; assign LA_CLOCK = 1'b0; assign LA_A2_0 = 1'b0; assign LA_A2_1 = 1'b0; assign LA_A2_2 = 1'b0; assign LA_A2_3 = 1'b0; assign LA_A2_4 = 1'b0; assign LA_A2_5 = 1'b0; assign LA_A2_6 = 1'b0; assign LA_A2_7 = 1'b0; assign LA_A3_0 = 1'b0; assign LA_A3_1 = 1'b0; assign LA_A3_2 = 1'b0; assign LA_A3_3 = 1'b0; assign LA_A3_4 = 1'b0; assign LA_A3_5 = 1'b0; assign LA_A3_6 = 1'b0; assign LA_A3_7 = 1'b0; assign LA_C3_4 = 1'b0; assign LA_C3_5 = 1'b0; assign LA_C3_6 = 1'b0; assign LA_C3_7 = 1'b0; assign ADC_IN = 1'bz; assign ADC_CS = 1'bz; assign ADC_CLK = 1'bz; assign BP_L1 = 1'bz; assign BP_ORBIT = 1'bz; assign OBP_BC = 1'bz; assign BP_L1_DATA = 1'bz; assign BP_L2_STROBE = 1'bz; assign BP_L0 = 1'bz; assign BP_PREPULSE = 1'bz; assign BP_L2_DATA = 1'bz; assign SPARE_1 = 1'bz; assign SPARE_2 = 1'bz; assign SPARE_3 = 1'bz; assign SPARE_4 = 1'bz; assign DWB = 1'bz; assign ADC_SDATA = 1'bz; assign IN_SPARE = 1'bz; assign IN_LVDS = 1'bz; assign IN_BUSY2 = 1'bz; assign MSTROBE = 1'bz; assign VME_CLK = 1'bz; assign CON_SPARE1 = 1'bz; assign CON_SPARE2 = 1'bz; assign CON_SPARE3 = 1'bz; assign CON_SPARE4 = 1'bz; endmodule