# The top level design name
design=LTU_T
revision=DSE
design_folder=Quartus-Files
# source files
prefix = ./SRC
prefix_ltu_m = $(prefix)/LTU_T_modules
counter = counter_syn.v
pll = PLL_syn.v
timer = $(prefix_ltu_m)/timer/timer_counter_syn.v $(prefix_ltu_m)/timer/timer.v
seqGen = $(prefix_ltu_m)/seqGen/counter_seqGen_syn.v $(prefix_ltu_m)/seqGen/seqGen.v
protocol_converter = $(prefix_ltu_m)/protocol_converter/protocol_converter_counter_syn.v $(prefix_ltu_m)/protocol_converter/protocol_converter.v
LED_controler = $(prefix_ltu_m)/LED_controler/time_counter_syn.v $(prefix_ltu_m)/LED_controler/input_counter_syn.v $(prefix_ltu_m)/LED_controler/LED_control.v $(prefix_ltu_m)/LED_controler/LED_control_RDWR.v
src_files = $(timer) $(prefix_ltu_m)/switch.v $(LED_controler) $(prefix_ltu_m)/communicator.v $(seqGen) $(prefix_ltu_m)/$(counter) $(prefix_ltu_m)/$(pll) $(protocol_converter) $(prefix_ltu_m)/synchronizerIn.v $(prefix)/$(design).v
# Testbench
prefix_tb = ./TestBench
#testbench = $(prefix_tb)/LTU_T-Testbench.v
testbench = $(prefix_tb)/LTU_T-Testbench-CTP.v
testbench_files = $(prefix_tb)/BC-clk.v $(prefix_tb)/FEE-GTU-emu.v $(prefix_tb)/CTP-LTU-emu.v

alt_sim = /home/trd/altera/13.0sp1/quartus/eda/sim_lib# the location of the Altera sim. models
alt_family = cyclone
alt_lib = $(alt_family)_components
net_para = ./Quartus-Files/simulation/modelsim/$(design).vo# netlist after place & route
sdf_alt = ./Quartus-Files/simulation/modelsim/$(design)_v.sdo# standard delay file (SDF)
$(alt_lib):
	vlib $@
	vlog -work $@ "$(alt_sim)/$(alt_family)_atoms.v"
	vcom -work $@ "$(alt_sim)/$(alt_family)_components.vhd"
	vmap $(alt_family) $@

# Compile the Source with Quartus
anasyn:
	python SRC/make_addresses.py
	quartus_map --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
partmerge:
	quartus_cdb --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision) --merge=on
fit:
	quartus_fit --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_asm --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_sta $(design_folder)/$(design) -c $(revision)
	quartus_eda --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_drc --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_pow --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
timing:
	python SRC/make_addresses.py
	quartus_map --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_cdb --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision) --merge=on
	quartus_fit --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_asm --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_sta $(design_folder)/$(design) -c $(revision)
rest:
	quartus_eda --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_drc --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_pow --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_cpf -c $(design_folder)/output_files/$(revision).sof $(design_folder)/output_files/$(design).rbf

convert:
	quartus_cpf -c $(design_folder)/output_files/$(revision).sof $(design_folder)/output_files/$(design).rbf

upload:
	scp $(design_folder)/output_files/$(design).rbf daq02:~/ltu/vme/CFG/ltu/.

all:
	python SRC/make_addresses.py
	quartus_map --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_cdb --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision) --merge=on
	quartus_fit --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_asm --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_sta $(design_folder)/$(design) -c $(revision)
	quartus_eda --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_drc --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_pow --read_settings_files=on --write_settings_files=off $(design_folder)/$(design) -c $(revision)
	quartus_cpf -c $(design_folder)/output_files/$(revision).sof $(design_folder)/output_files/$(design).rbf

flash:
	ssh daq02 ./ltu/scripts/loadLTUfpga $(design).rbf 0x813000
# Compile the source for functional simulation
functional: $(src_files)
	vlib $@
	vlog -work $@ $(src_files)

# Functional Simulation
simfunInp: $(testbench) $(testbench_files) functional
	vlib testbench
	vmap testbench functional
	vlog -work testbench $(testbench_files) $(testbench)
	vsim -L altera_mf -L cyclone_ver -L lpm_ver -L testbench testbench.TestBench -t 1ps -do '$(prefix_tb)/InputOutput.do'

simfunSeq: $(testbench) $(testbench_files) functional
	vlib testbench
	vmap testbench functional
	vlog -work testbench $(testbench_files) $(testbench)
	vsim -L altera_mf -L cyclone_ver -L lpm_ver -L testbench testbench.TestBench -t 1ps -do '$(prefix_tb)/seqGen.do'

simfun: $(testbench) $(testbench_files) functional
	vlib testbench
	vmap testbench functional
	vlog -work testbench $(testbench_files) $(testbench)
	vsim -L altera_mf -L cyclone_ver -L lpm_ver -L testbench testbench.TestBench -t 1ps

simSeqGen: $(prefix_tb)/seqGen-Testbench.v $(prefix_tb)/BC-clk.v $(prefix_tb)/fast-clk.v functional
	vlib testbench
	vmap testbench functional
	vlog -work testbench $(prefix_tb)/seqGen-Testbench.v $(prefix_tb)/BC-clk.v $(prefix_tb)/fast-clk.v
	vsim -L altera_mf -L cyclone_ver -L lpm_ver -L testbench testbench.TestBench -t 1ps -do '$(prefix_tb)/seqGen.do'

simSeqGenBM: $(prefix_tb)/seqGen-Testbench.v $(prefix_tb)/BC-clk.v $(prefix_tb)/fast-clk.v functional
	vlib SeqGen-testbench
	vmap SeqGen-testbench functional
	vlog -work SeqGen-testbench $(prefix_tb)/seqGen-Testbench.v $(prefix_tb)/BC-clk.v $(prefix_tb)/fast-clk.v
	vsim -c -wlf $(prefix_tb)/seqGen.wlf -L altera_mf -L cyclone_ver -L lpm_ver -L SeqGen-testbench SeqGen-testbench.TestBench -t 1ps -do '$(prefix_tb)/seqGenBM.do'

simTimer: $(prefix_tb)/timer-Testbench.v $(prefix_tb)/fast-clk.v functional
	vlib testbench
	vmap testbench functional
	vlog -work testbench $(prefix_tb)/timer-Testbench.v $(prefix_tb)/fast-clk.v
	vsim -L altera_mf -L cyclone_ver -L lpm_ver -L testbench testbench.TestBench -t 1ps -do '$(prefix_tb)/timer.do'

simPC: $(prefix_tb)/protocol_converter-Testbench.v $(prefix_tb)/fast-clk.v $(prefix_tb)/BC-clk.v functional
	vlib testbench
	vmap testbench functional
	vlog -work testbench $(prefix_tb)/protocol_converter-Testbench.v $(prefix_tb)/fast-clk.v $(prefix_tb)/BC-clk.v
	vsim -L altera_mf -L cyclone_ver -L lpm_ver -L testbench testbench.TestBench -t 1ps -do '$(prefix_tb)/protocol_converter.do'

simLED: $(prefix_tb)/LED_controler-Testbench.v $(prefix_tb)/fast-clk.v $(prefix_tb)/BC-clk.v functional
	vlib testbench
	vmap testbench functional
	vlog -work testbench $(prefix_tb)/LED_controler-Testbench.v $(prefix_tb)/fast-clk.v $(prefix_tb)/BC-clk.v
	vsim -L altera_mf -L cyclone_ver -L lpm_ver -L testbench testbench.TestBench -t 1ps -do '$(prefix_tb)/LED_controler.do'

simLEDBM: $(prefix_tb)/LED_controler-Testbench.v $(prefix_tb)/fast-clk.v $(prefix_tb)/BC-clk.v functional
	vlib LED_controler-testbench
	vmap LED_controler-testbench functional
	vlog -work LED_controler-testbench $(prefix_tb)/LED_controler-Testbench.v $(prefix_tb)/fast-clk.v $(prefix_tb)/BC-clk.v
	vsim -c -wlf $(prefix_tb)/LED_controler.wlf -L altera_mf -L cyclone_ver -L lpm_ver -L LED_controler-testbench LED_controler-testbench.TestBench -t 1ps -do '$(prefix_tb)/LED_controlerBM.do'

# Clean all library directories
clean:
	rm -rf functional/ testbench/ LTU-T.vcd transcript modelsim.ini vsim.wlf cyclone_components/ layouta/ work/
	ls -l --color=auto

layouta: $(alt_lib) $(net_para)
	vlib $@; vlog -work $@ $(net_para)
# Simulate the p & r netlist without timing backannotation
simlay: $(testbench) $(testbench_files) layouta functional
	vmap libdut testbench
	vmap libdut layouta
	vmap libdut functional
	rm -rf work; vlib libdut
	vlog -work libdut $(testbench_files) $(testbench) $(alt_family)_components
	vsim 'libdut.TestBench' -t 1ps -do '$(prefix_tb)/InputOutput.do'