# $Id$:

# all sources for synthesis

pref_top_spi=./SRC
src_top_spi = \
$(pref_top_spi)/error_decoder.vhd          \
$(pref_top_spi)/hamming_enc.vhd            \
$(pref_top_spi)/hamming_dec.vhd            \
$(pref_top_spi)/inp_sync.vhd               \
$(pref_top_spi)/act_check.vhd              \
$(pref_top_spi)/mclk_prescaler.vhd         \
$(pref_top_spi)/switch_bus_mux.vhd         \
$(pref_top_spi)/swbus_reg.vhd              \
$(pref_top_spi)/spi_deser_ham_dec.vhd      \
$(pref_top_spi)/spi_deserialiser.vhd       \
$(pref_top_spi)/spi_input_synchroniser.vhd \
$(pref_top_spi)/pwm.vhd                    \
$(pref_top_spi)/led_module.vhd             \
$(pref_top_spi)/top.vhd

# all sources for simulation

pref_top_sim=./SIM/SRC
src_top_sim = \
$(pref_top_spi)/hamming_enc.vhd    \
$(pref_top_spi)/hamming_dec.vhd    \
$(pref_top_sim)/spi_master.vhd     \
$(pref_top_sim)/fdiv.vhd           \
$(pref_top_sim)/shreg_parin.vhd    \
$(pref_top_sim)/shreg.vhd          \
$(pref_top_sim)/spi_master_dcs.vhd \
$(pref_top_sim)/top_tb.vhd