-- $Id$: -- Last updated: 2012.08.24 -- VERSION 1.10 up library ieee; use ieee.std_logic_1164.all; library igloo; -- ================================================ -- Top file for SPI switch to Ethernet entity top is port ( reset_n : in std_logic; -- reset input xclk_in : in std_logic; -- master clock 100kHz spi_clki_1 : in std_logic; -- spi 0 clock input spi_stri_1 : in std_logic; -- spi 0 strobe input spi_din_1 : in std_logic; -- spi 0 data input spi_dout_1 : out std_logic; -- spi 0 data output spi_clki_2 : in std_logic; -- spi 0 clock input spi_stri_2 : in std_logic; -- spi 0 strobe input spi_din_2 : in std_logic; -- spi 0 data input spi_dout_2 : out std_logic; -- spi 0 data output SW_UP : in std_logic; SW_DN : in std_logic; A_sel : out std_logic_vector( 12 downto 1); B_sel : out std_logic_vector( 12 downto 1); -- 1,2,3 - front side, next to the man switch -- 4,5 JTAG -- 6,7 -- spi LED : out std_logic_vector(7 downto 1); LED_jtag_const : out std_logic_vector(5 downto 4); j2_spare : out std_logic_vector(5 downto 0); j4_spare : out std_logic_vector(8 downto 0) ); end top; -- ================================================ architecture a of top is -- ================================================================================= -- Declare used components: -- ================================================ --clock buffer component CLKBUF is port( PAD : in std_logic; Y : out std_logic ); end component; -- Crystal clock prescaler for 100kHz SPI sampling clock -- Crystal clock is 4 MHz component mclk_prescaler port ( reset_n : in std_logic; -- reset input rst_out : out std_logic; -- reset input xclk_in : in std_logic; -- clock input mclk : out std_logic -- prescaler output ); end component; -- ================================================ -- SPI deserialiser and hamming decoder channel module component spi_deser_ham_dec generic(my_channel : Integer range 0 to 1 := 0); port ( mrst : in std_logic; -- master reset mclk : in std_logic; -- master clock 100kHz act_otherc : in std_logic_vector( 2 downto 0); hm_stat_summ : in std_logic_vector( 2 downto 1); selected_ch : in std_logic; other_ch : in std_logic_vector(23 downto 0); debug : out std_logic_vector(2 downto 0); spi_clki : in std_logic; -- spi clock input spi_stri : in std_logic; -- spi strobe input spi_din : in std_logic; -- spi data input spi_dout : out std_logic; -- spi data output ham_data_out : out std_logic_vector (23 downto 0); -- decoded hamming data bus valid : out std_logic; ham_err : out std_logic_vector( 1 downto 0); -- hamming error signal 1_0 port_act_out : out std_logic_vector( 2 downto 0) -- clock and strobe signal activity signal ); end component; -- ================================================ -- Error decoder -- Error decoder decides what to do if any hamming decoder failed component error_decoder port ( -- mrst : in std_logic; -- master reset -- mclk : in std_logic; -- master clock 100kHz -- state => 00 = ok; 01 = parity error; 10 = 2-Bit error; 11 1-Bit error (corrected) valid : in std_logic_vector(2 downto 1); -- bit 31 ham_err_summ : in std_logic_vector(2 downto 1); spi_act_all : in std_logic_vector(2 downto 1); bus_mux_sel : out std_logic; -- bus multiplexer output signal out_reg_strobe : out std_logic -- output register strobe output signal ); end component; -- ================================================================================= -- Switch Output multiplexer component switch_bus_mux generic (N : Integer := 24); port ( mux_data_in_1 : in std_logic_vector( N-1 downto 0); mux_data_in_2 : in std_logic_vector( N-1 downto 0); mux_data_out : out std_logic_vector( N-1 downto 0); mux_select : in std_logic -- ); end component; -- ================================================ -- Ethernet switch bus output register component swbus_reg generic (N : Integer := 24); port ( mrst : in std_logic; -- reset input mclk : in std_logic; -- master clock 100kHz oreg_strobe : in std_logic; -- output register strobe clock swbus_reg_in : in std_logic_vector(N-1 downto 0); swbus_reg_out : out std_logic_vector(N-1 downto 0) ); end component; component led_module is port ( mclk : in std_logic;-- prescaler output mrst : in std_logic; sw_sel : in std_logic_vector( 1 downto 0); ham_err_summ : in std_logic_vector( 2 downto 1); spi_act_all : in std_logic_vector( 2 downto 1); eth_switch_bus : in std_logic_vector(23 downto 0); bus_mux_sel : in std_logic; out_reg_strobe : in std_logic; -- output register strobe output signal -- valid : in std_logic_vector( 2 downto 1); led_out : out std_logic_vector( 7 downto 1) ); end component; -- Internal signals signal mclk : std_logic; signal mrst : std_logic; signal spi_act_1 : std_logic_vector( 2 downto 0); signal spi_act_2 : std_logic_vector( 2 downto 0); signal spi_act_all : std_logic_vector( 2 downto 1); signal ham_err_1 : std_logic_vector( 1 downto 0); signal ham_err_2 : std_logic_vector( 1 downto 0); signal ham_err_summ : std_logic_vector( 2 downto 1); signal bus_mux_sel : std_logic; signal out_reg_strobe : std_logic; signal mux_data_in_1 : std_logic_vector(23 downto 0); signal mux_data_in_2 : std_logic_vector(23 downto 0); signal mux_data_out : std_logic_vector(23 downto 0); signal eth_switch_bus : std_logic_vector(23 downto 0); signal sw_sel : std_logic_vector( 1 downto 0); signal valid : std_logic_vector( 2 downto 1); signal debug1 : std_logic_vector( 2 downto 0); signal debug2 : std_logic_vector( 2 downto 0); signal xclk_in_i : std_logic; begin LED_jtag_const <= "00"; -- ------------------------------------------------------------------------- --clock buffer cbuf_qclk: CLKBUF port map( PAD => xclk_in, Y => xclk_in_i); Inst_prescl_1: mclk_prescaler port map ( reset_n => reset_n, rst_out => mrst, xclk_in => xclk_in_i, mclk => mclk ); -- ------------------------------------------------------------------------- Inst_channel_1: spi_deser_ham_dec generic map(my_channel => 0) port map ( mrst => mrst, mclk => mclk, act_otherc => spi_act_2, hm_stat_summ => ham_err_summ, selected_ch => bus_mux_sel, other_ch => mux_data_in_2, debug => debug1, spi_clki => spi_clki_1, spi_stri => spi_stri_1, spi_din => spi_din_1, spi_dout => spi_dout_1, ham_data_out => mux_data_in_1, valid => valid(1), ham_err => ham_err_1, port_act_out => spi_act_1 ); Inst_channel_2: spi_deser_ham_dec generic map(my_channel => 1) port map ( mrst => mrst, mclk => mclk, act_otherc => spi_act_1, hm_stat_summ => ham_err_summ, selected_ch => bus_mux_sel, other_ch => mux_data_in_1, debug => debug2, spi_clki => spi_clki_2, spi_stri => spi_stri_2, spi_din => spi_din_2, spi_dout => spi_dout_2, ham_data_out => mux_data_in_2, valid => valid(2), ham_err => ham_err_2, port_act_out => spi_act_2 ); ham_err_summ(1) <= '0' when ham_err_1 = "00" else '1'; ham_err_summ(2) <= '0' when ham_err_2 = "00" else '1'; spi_act_all(1) <= '1' when spi_act_1="111" else '0'; spi_act_all(2) <= '1' when spi_act_2="111" else '0'; -- ------------------------------------------------------------------------- Inst_bus_mux: switch_bus_mux generic map(N => mux_data_out'length) port map ( mux_data_in_1 => mux_data_in_1, mux_data_in_2 => mux_data_in_2, mux_data_out => mux_data_out, mux_select => bus_mux_sel ); -- ------------------------------------------------------------------------- Inst_bus_outreg: swbus_reg generic map(N => mux_data_out'length) port map ( mrst => mrst, mclk => mclk, oreg_strobe => out_reg_strobe, swbus_reg_in => mux_data_out, swbus_reg_out => eth_switch_bus ); -- ------------------------------------------------------------------------- Inst_err_dec: error_decoder port map ( -- mrst => mrst, -- mclk => mclk, valid => valid, ham_err_summ => ham_err_summ, spi_act_all => spi_act_all, bus_mux_sel => bus_mux_sel, out_reg_strobe => out_reg_strobe ); -- ========================================================================= -- Processes: -- ========================================================================= -- ================================================ sw_sel <= SW_UP & SW_DN; with sw_sel select A_sel <= eth_switch_bus(11 downto 0) when "11", (others => '1') when "10", (others => '0') when "01", (others => '-') when others; with sw_sel select B_sel <= eth_switch_bus(23 downto 12) when "11", (others => '1') when "10", (others => '0') when "01", (others => '-') when others; -- ================================================ leds: led_module port map ( mclk => mclk, mrst => mrst, sw_sel => sw_sel, ham_err_summ => ham_err_summ, spi_act_all => spi_act_all, eth_switch_bus => eth_switch_bus, bus_mux_sel => bus_mux_sel, out_reg_strobe => out_reg_strobe, -- valid => valid, led_out => LED); -- ================================================ j2_spare(5 downto 0) <= debug2 & debug1; j4_spare(8 downto 0) <= (others => '0'); -- ================================================ end;