-- $Id$:

-- Output Multiplexer for the two 32 bit busses

-- Version 1.10 up

-- Last updated: 2012.08.24

-- ---------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

--------------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------------


entity switch_bus_mux is
generic (N : Integer := 24);
        port
        (
        mux_data_in_1   : in    std_logic_vector( N-1 downto 0);
        mux_data_in_2   : in    std_logic_vector( N-1 downto 0);
        mux_data_out    : out   std_logic_vector( N-1 downto 0);
        mux_select      : in    std_logic --
        );
end switch_bus_mux;


--------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------

architecture a of switch_bus_mux is

-- signal  : std_logic;


begin

mux_data_out <= mux_data_in_1 when mux_select = '0' else mux_data_in_2;

end;


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