-- $Id$:

-- Output Register for the 32 bit ethernet switch bus

-- Version 1.10 up

-- Last updated 2012.08.24

-- ---------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

--------------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------------


entity swbus_reg is

generic (N : Integer := 24);
        port
        (
        mrst                : in    std_logic; -- reset input
        mclk                : in    std_logic; -- master clock 100kHz
        oreg_strobe         : in    std_logic; -- output register strobe clock

        swbus_reg_in        : in    std_logic_vector(N-1 downto 0);
        swbus_reg_out       : out   std_logic_vector(N-1 downto 0)
        );

        end swbus_reg;


--------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------

architecture a of swbus_reg is

-- signal  : std_logic;


begin

strobe_data: process(mclk)

begin

        if rising_edge(mclk) then

            if mrst = '1' then
                swbus_reg_out <= (others => '0');
            elsif oreg_strobe = '1' then
                swbus_reg_out <= swbus_reg_in;
            end if;

        end if;

end process;

end;


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