-- $Id$:

--      Last updated: 2012.06.24

library ieee;
use ieee.std_logic_1164.all;


-- ================================================

entity spi_input_synchroniser is
port
        (
        mclk            : in std_logic; -- master clock 100kHz

        spi_clk_in      : in std_logic; -- spi clock input
        spi_str_in      : in std_logic; -- spi strobe input
        spi_data_in     : in std_logic; -- spi data input

        spi_clko_sync   : out std_logic; -- spi clock input
        spi_stro_sync   : out std_logic; -- spi strobe input
        spi_datao_sync  : out std_logic; -- spi data output

        port_act_out    : out std_logic_vector(2 downto 0) -- spi clock signal activity output
        );

end spi_input_synchroniser;


-- ================================================

architecture a of spi_input_synchroniser is

component inp_sync is
generic (N : Integer := 3);
        port
        (
        inp             : in  std_logic;
        clk             : in  std_logic;
        q               : out std_logic;
        posedge         : out std_logic;
        negedge         : out std_logic
        );

end component;

component act_check is
generic (N : Integer := 3);
        port
        (
        inp             : in  std_logic;
        clk             : in  std_logic;
        activ           : out std_logic
        );

end component;

constant Nfilt : Integer := 3;
constant FSYS  : Integer := 1;

signal spi_stro_sync_i  : std_logic;
signal spi_datao_sync_i : std_logic;
signal spi_sclk_sync_i  : std_logic;

signal activ_sclk       : std_logic;
signal activ_sstr       : std_logic;
signal activ_sdat       : std_logic;


-- ================================================

begin

sync_clk: inp_sync
generic map(N => Nfilt)
        port map
        (
        inp             => spi_clk_in,
        clk             => mclk,
        q               => spi_sclk_sync_i,
        posedge         => spi_clko_sync,
        negedge         => open);


sync_dat: inp_sync
generic map(N => Nfilt)
        port map
        (
        inp             => spi_data_in,
        clk             => mclk,
        q               => spi_datao_sync_i,
        posedge         => open,
        negedge         => open);

        spi_datao_sync <= spi_datao_sync_i;

sync_str: inp_sync
generic map(N => Nfilt)
        port map
        (
        inp             => spi_str_in,
        clk             => mclk,
        q               => spi_stro_sync_i,
        posedge         => open,
        negedge         => open);

        spi_stro_sync  <= spi_stro_sync_i;

acheck_clk: act_check
generic map(N => 200*FSYS)
        port map
        (
        inp             => spi_sclk_sync_i,
        clk             => mclk,
        activ           => activ_sclk
        );

acheck_str: act_check
generic map(N => 200*40*FSYS)
        port map
        (
        inp             => spi_stro_sync_i,
        clk             => mclk,
        activ           => activ_sstr
        );

acheck_dat: act_check
generic map(N => 200*40*FSYS)
        port map
        (
        inp             => spi_datao_sync_i,
        clk             => mclk,
        activ           => activ_sdat
        );


-- Detect activity by signal edges

    port_act_out <= activ_sclk & activ_sstr & activ_sdat;

-- ================================================

end;