-- $Id$: -- Last updated: 2012.08.24 -- Version 1.10 library ieee; use ieee.std_logic_1164.all; -- ================================================ entity spi_deserialiser is port ( mrst : in std_logic; -- master reset mclk : in std_logic; -- master clock 100kHz spi_par_back_in : in std_logic_vector(38 downto 0); spi_clk_en : in std_logic; -- spi clock input spi_str_in : in std_logic; -- spi strobe input spi_data_in : in std_logic; -- spi data input spi_data_out : out std_logic; -- spi data output spi_par_out : out std_logic_vector(38 downto 0) ); end spi_deserialiser; -- ================================================ architecture a of spi_deserialiser is signal spi_par_out_0 : std_logic_vector( 38 downto 0); signal spi_par_back : std_logic_vector( 38 downto 0); signal toggle : std_logic; -- ================================================ begin -- shift in and out data : shift_data_in: process(mclk, mrst) begin if rising_edge(mclk) then if mrst = '1' then spi_par_out <= (others => '0'); spi_par_out_0 <= (others => '0'); spi_par_back <= (others => '0'); toggle <= '0'; elsif spi_clk_en = '1' then --spi_data_out <= spi_par_out_0(38); spi_par_out_0 <= spi_par_out_0(37 downto 0) & spi_data_in; spi_par_back <= spi_par_back (37 downto 0) & (toggle and not spi_str_in); toggle <= not toggle; if spi_str_in = '1' then spi_par_out <= spi_par_out_0; spi_par_back <= spi_par_back_in; toggle <= '1'; end if; end if; end if; end process; spi_data_out <= spi_par_back(38); -- ================================================ end;