-- $Id$:

--      Last updated: 2012.08.24

-- VERSION 1.10

library ieee;
use ieee.std_logic_1164.all;

-- -------------------------------------------------------------

-- SINGLE SPI DECODE AND HAMMING CHECKER CHANNEL

-- Contains following modules:

-- 1. spi signal syncroniser + spi clock and spi strobe activity checker/flag
-- 2. 39 bit spi shift register with output register
-- 3. hamming decoder with error output signals

-- This module just connects the synchroniser to the deserialiser and the
-- deserialiser to the hamming decoder.
-- No processes done here.


-- ================================================

-- One channel module for SPI deserialiser and hamming decoder

entity spi_deser_ham_dec is
generic(my_channel : Integer range 0 to 1 := 0);
port
  (
        mrst            : in    std_logic; -- master reset
        mclk            : in    std_logic; -- master clock 100kHz

        act_otherc      : in    std_logic_vector( 2 downto 0);
        hm_stat_summ    : in    std_logic_vector( 2 downto 1);
        selected_ch     : in    std_logic;
        other_ch        : in    std_logic_vector(23 downto 0);

        debug           : out   std_logic_vector( 2 downto 0);


        spi_clki        : in    std_logic; -- spi clock input
        spi_stri        : in    std_logic; -- spi strobe input
        spi_din         : in    std_logic; -- spi data input
        spi_dout        : out   std_logic; -- spi data output

        ham_data_out    : out   std_logic_vector(23 downto 0);
        valid           : out   std_logic;
        ham_err         : out   std_logic_vector( 1 downto 0); --

        port_act_out    : out   std_logic_vector( 2 downto 0)  -- spi clock signal activity output
  );

end spi_deser_ham_dec;


-- ================================================

architecture a of spi_deser_ham_dec is


-- =================================================================================

-- Declare used components:

-- =================================================================================


-- SPI input snchroniser module + spi clock and spi strobe activity checker/flag

component spi_input_synchroniser

  port
    (
    mclk                : in std_logic; -- master clock 100kHz

    spi_clk_in          : in std_logic; -- spi clock input
    spi_str_in          : in std_logic; -- spi strobe input
    spi_data_in         : in std_logic; -- spi data input

    spi_clko_sync       : out std_logic; -- spi clock input
    spi_stro_sync       : out std_logic; -- spi strobe input
    spi_datao_sync      : out std_logic; -- spi data output

    port_act_out        : out std_logic_vector(2 downto 0) -- spi clock signal activity output
    );

end component;


-- ================================================

-- SPI deserialiser module

component spi_deserialiser

  port
    (
        mrst            : in    std_logic; -- master reset
        mclk            : in    std_logic; -- master clock 100kHz

        spi_par_back_in : in    std_logic_vector(38 downto 0);

        spi_clk_en      : in    std_logic; -- spi clock input
        spi_str_in      : in    std_logic; -- spi strobe input
        spi_data_in     : in    std_logic; -- spi data input
        spi_data_out    : out   std_logic; -- spi data output

        spi_par_out     : out   std_logic_vector(38 downto 0)
    );

end component;


-- ================================================

-- Hamming decoder
-- Input data bus is 39 bit

component hamming_dec

  port
        (
        din     : in  std_logic_vector (38 downto 0);  -- data input from spi deserialiser
        dout    : out std_logic_vector (31 downto 0);  -- data output
        state   : out std_logic_vector ( 1 downto 0)   -- error status 1..0
        );

end component;

component hamming_enc is
    port (
          din   : in  std_logic_vector (31 downto 0);  -- data from the device
          dout  : out std_logic_vector (38 downto 0)   -- data to instr. memory
          );
end component;

signal spi_clk_s        : std_logic;
signal spi_strobe_s     : std_logic;
signal spi_data_s       : std_logic;

signal spi_par_out      : std_logic_vector(38 downto 0);
signal spi_par_back_hm  : std_logic_vector(38 downto 0);
signal spi_par_back     : std_logic_vector(31 downto 0);
signal ham_data_out_i   : std_logic_vector(31 downto 0);
signal my_ch            : std_logic;

begin
    my_ch <= '1' when my_channel = 1 else '0';

-- =========================================================================

--      Instantiate and connect the modules (components):

-- =========================================================================
-- Connect SPI synchroniser

Inst_spi_sync: spi_input_synchroniser

  port map
        (
        -- common inputs
        mclk            => mclk,

        -- connect syncroniser inputs to module inputs
        spi_clk_in      => spi_clki,
        spi_str_in      => spi_stri,
        spi_data_in     => spi_din,

        -- syncroniser output connections to the shift register
        spi_clko_sync   => spi_clk_s,
        spi_stro_sync   => spi_strobe_s,
        spi_datao_sync  => spi_data_s,

        -- activity signal to led output
        port_act_out    => port_act_out
        );

    debug <= spi_clk_s & spi_strobe_s & spi_data_s;

-- ================================================

-- Connect spi deserialiser

Inst_spi_deser: spi_deserialiser

  port map
        (
        -- common inputs
        mrst            => mrst,
        mclk            => mclk,

        spi_par_back_in => spi_par_back_hm,

        spi_clk_en      => spi_clk_s,
        spi_str_in      => spi_strobe_s,
        spi_data_in     => spi_data_s,
        spi_data_out    => spi_dout,

        spi_par_out     => spi_par_out
        );


-- ================================================

-- Connect hamming decoder

Inst_hamming_dec: hamming_dec

  port map
        (
        din      => spi_par_out,
        dout     => ham_data_out_i,
        state    => ham_err
        );

    valid <= ham_data_out_i(ham_data_out_i'high);
    ham_data_out <= ham_data_out_i(ham_data_out'range);


    process(act_otherc, hm_stat_summ, selected_ch, other_ch, ham_data_out_i)
    begin

        spi_par_back <= ham_data_out_i;

        spi_par_back(29 downto 24) <= selected_ch & hm_stat_summ & act_otherc;

        if ham_data_out_i(30)='0' and (my_ch /= selected_ch) then
            spi_par_back(23 downto 0) <= other_ch;
        end if;

    end process;

henc: hamming_enc
    port map(
          din   => spi_par_back,
          dout  => spi_par_back_hm);

end;