-- $Id$:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

--------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------

entity pwm is

        port
        (
        mclk            : in  std_logic;-- prescaler output
        mrst            : in  std_logic;
        led_in          : in  std_logic_vector(7 downto 1); -- prescaler output
        led_out         : out std_logic_vector(7 downto 1) -- prescaler output
        );

        end pwm;


--------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------

architecture a of pwm is


signal shreg : std_logic_vector(5 downto 1);

begin
    process(mclk)
    begin
        if rising_edge(mclk) then
            if mrst = '1' then
                shreg <= "00001";
            else
                shreg <= shreg(4 downto 1) & shreg(5);
            end if;
            led_out(7 downto 6) <= shreg(5 downto 4) and led_in(7 downto 6);
            led_out(3 downto 1) <= shreg(3 downto 1) and led_in(3 downto 1);
            led_out(5 downto 4) <= led_in(5 downto 4);
        end if;
    end process;

end;