-- $Id$:

-- This prescaler divides the incomming crystal clock of 4MHz down to
-- 100kHz sampling clock for the spi handling etc. (1/40)

-- Version 1.10 up

-- Last updated: 2012.08.24

-- ---------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

--------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------

entity mclk_prescaler is

        port
        (
        reset_n         : in  std_logic; -- reset input
        rst_out         : out std_logic; -- reset input
        xclk_in         : in  std_logic; -- clock input
        mclk            : out std_logic -- prescaler output
        );

        end mclk_prescaler;


--------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------

architecture a of mclk_prescaler is

component inp_sync is
generic (N : Integer := 3);
        port
        (
        inp             : in  std_logic;
        clk             : in  std_logic;
        q               : out std_logic;
        posedge         : out std_logic;
        negedge         : out std_logic
        );

end component;

subtype counter_range is Integer range 0 to 3;
signal counter : counter_range := 0;

signal slow_rst : std_logic;
signal posedge_r: std_logic;
signal negedge_r: std_logic;

begin

rst_sync: inp_sync
generic map(N => 10)
        port map
        (
        inp             => reset_n,
        clk             => xclk_in,
        q               => open,
        posedge         => posedge_r,
        negedge         => negedge_r);

prescaler: process(xclk_in)

    begin

        if rising_edge(xclk_in) then

            if posedge_r='1' or negedge_r='1' then
                mclk <= '1';
                counter <= 0;
                slow_rst <= '1';
            else

                if counter = counter_range'high then
                    mclk <= '1';
                    counter <= 0;

                else
                    counter <= counter + 1;
                    if counter = counter_range'high/2 then
                        mclk <= '0';
                    end if;
                end if;

                if counter = counter_range'high/4 then
                    rst_out <= slow_rst;
                    slow_rst <= '0';
                end if;
            end if;

        end if;

    end process;

end;


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