-- $Id$:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

--------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------

entity led_module is

        port
        (
        mclk            : in  std_logic;-- prescaler output
        mrst            : in  std_logic;

        sw_sel          : in  std_logic_vector( 1 downto 0);

        spi_act_all     : in  std_logic_vector( 2 downto 1);

        ham_err_summ    : in  std_logic_vector( 2 downto 1);

        eth_switch_bus  : in  std_logic_vector(23 downto 0);

        bus_mux_sel     : in  std_logic;

        out_reg_strobe  : in  std_logic; -- output register strobe output signal

--        valid           : in  std_logic_vector( 2 downto 1);

        led_out         : out std_logic_vector( 7 downto 1)
        );

end led_module;


--------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------

architecture a of led_module is

component pwm is

        port
        (
        mclk            : in  std_logic;-- prescaler output
        mrst            : in  std_logic;
        led_in          : in  std_logic_vector(7 downto 1);
        led_out         : out std_logic_vector(7 downto 1)
        );

        end component;

signal   cntdiv   : std_logic_vector(18 downto 0);
constant cntdivs : std_logic_vector(cntdiv'high-4 downto 0) := (others => '1');

signal   gate1of4 : std_logic;
signal   gate2of4 : std_logic;
--signal   gate20ms : std_logic;

signal   led_in   : std_logic_vector(7 downto 1);

constant eth_all1 : std_logic_vector(eth_switch_bus'range) := (others => '1');
constant eth_all0 : std_logic_vector(eth_switch_bus'range) := (others => '0');

signal   sel_all1 : std_logic;
signal   sel_all0 : std_logic;

begin

    gate1of4 <= cntdiv(cntdiv'high) and cntdiv(cntdiv'high-1);
    gate2of4 <= cntdiv(cntdiv'high);

    process(mclk)
    begin
        if rising_edge(mclk) then
            cntdiv <= cntdiv + 1;
--          if cntdiv(cntdivs'range) = cntdivs then gate20ms <= '1';
--                                             else gate20ms <= '0'; end if;
        end if;
    end process;

    sel_all1 <= '1' when eth_switch_bus = eth_all1 else '0';
    sel_all0 <= '1' when eth_switch_bus = eth_all0 else '0';

    -- power
    led_in(1) <= '1';

    -- on    : ok, active, valid, selected
    -- blink : ok, active, not selected

    led_in(2) <= spi_act_all(1) and (not ham_err_summ(1)) and (gate1of4 or     bus_mux_sel or not out_reg_strobe);
    led_in(3) <= spi_act_all(2) and (not ham_err_summ(2)) and (gate1of4 or not bus_mux_sel or not out_reg_strobe);

    -- SW_DN = 0 : all 1
    -- SW_UP = 0 : all 0
    -- sw_sel <= SW_UP & SW_DN;

    led_in(4) <= gate2of4 when sw_sel(0) = '0' else '0' when sw_sel(1)='0' else sel_all1;
    led_in(5) <= gate2of4 when sw_sel(1) = '0' else '0' when sw_sel(0)='0' else sel_all0;

    -- back side, same as 2 and 3, the order might be wrong!
    led_in(6) <= led_in(2);
    led_in(7) <= led_in(3);

pwm_i: pwm
        port map
        (
        mclk            => mclk,
        mrst            => mrst,
        led_in          => led_in,
        led_out         => led_out);

end;