-- $Id$:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

--------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------

entity inp_sync is
generic (N : Integer := 3);
        port
        (
        inp             : in  std_logic;
        clk             : in  std_logic;
        q               : out std_logic;
        posedge         : out std_logic;
        negedge         : out std_logic
        );

end inp_sync;


--------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------

architecture a of inp_sync is

signal pipe     : std_logic_vector(N-1 downto 0);
constant pipe1  : std_logic_vector(N-1 downto 0) := (others => '1');
constant pipe0  : std_logic_vector(N-1 downto 0) := (others => '0');

signal int_q    : std_logic;


begin
    process(clk)
    begin
        if rising_edge(clk) then
            posedge <= '0';
            negedge <= '0';
            pipe <= pipe(pipe'high-1 downto 0) & inp;
            if pipe = pipe1 then
                int_q <= '1';
                posedge  <= not int_q;
            end if;
            if pipe = pipe0 then
                int_q <= '0';
                negedge  <= int_q;
            end if;
        end if;
    end process;
    q <= int_q;

end;