-- $Id$:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

--------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------

entity act_check is
generic (N : Integer := 3);
        port
        (
        inp             : in  std_logic;
        clk             : in  std_logic;
        activ           : out std_logic
        );

end act_check;


--------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------

architecture a of act_check is

signal cnt      : Integer range 0 to N;

signal inp_old  : std_logic;


begin
    process(clk)
    begin
        if rising_edge(clk) then
            inp_old <= inp;
            if inp_old /= inp then
                cnt <= N;
                activ <= '1';
            elsif cnt > 0 then
                cnt <= cnt - 1;
            else
                activ <= '0';
            end if;
        end if;
    end process;

end;