-- $Id$:

library ieee;
use ieee.std_logic_1164.all;

library fpga;

-- ================================================

-- Top file for SPI switch to Ethernet

entity top_tb is
generic (Td2 : time := 125 ns);
end top_tb;

architecture sim of top_tb is

component top is
  port
        (
        reset_n         : in  std_logic; -- reset input
        xclk_in         : in  std_logic; -- master clock 100kHz

        spi_clki_1      : in  std_logic; -- spi 0 clock input
        spi_stri_1      : in  std_logic; -- spi 0 strobe input
        spi_din_1       : in  std_logic; -- spi 0 data input
        spi_dout_1      : out std_logic; -- spi 0 data output

        spi_clki_2      : in  std_logic; -- spi 0 clock input
        spi_stri_2      : in  std_logic; -- spi 0 strobe input
        spi_din_2       : in  std_logic; -- spi 0 data input
        spi_dout_2      : out std_logic; -- spi 0 data output

--        eth_switch_bus  : out std_logic_vector( 31 downto 0);
        SW_UP           : in  std_logic;
        SW_DN           : in  std_logic;

        A_sel           : out std_logic_vector( 12 downto 1);
        B_sel           : out std_logic_vector( 12 downto 1);

        LED             : out std_logic_vector(7 downto 1);
        LED_jtag_const  : out std_logic_vector(5 downto 4);

        j2_spare        : out std_logic_vector(5 downto 0);
        j4_spare        : out std_logic_vector(8 downto 0)
        );

end component;

component spi_master is
generic (Td2 : time := 50 us;
         startpos : Natural := 1);
    port (
        valid         : in  std_logic; -- bit31
        spi_clko      : out std_logic; -- spi 0 clock input
        spi_stro      : out std_logic; -- spi 0 strobe input
        spi_din       : in  std_logic; -- spi 0 data input
        spi_dout      : out std_logic); -- spi 0 data output
end component;

component spi_master_dcs is
generic (Td2 : time := 50 us; -- for 10 kHz
         startpos : Natural := 1);
    port (
        valid         : in  std_logic; -- bit31
        spi_clko      : out std_logic; -- spi 0 clock input
        spi_stro      : out std_logic; -- spi 0 strobe input
        spi_din       : in  std_logic; -- spi 0 data input
        spi_dout      : out std_logic); -- spi 0 data output
end component;

--procedure


-- ================================================

-- Internal signals
signal  rst_n           : std_logic; -- reset input
signal  xclk_in         : std_logic := '1'; -- master clock 100kHz

signal  spi_clki_1      : std_logic; -- spi 0 clock input
signal  spi_stri_1      : std_logic; -- spi 0 strobe input
signal  spi_din_1       : std_logic; -- spi 0 data input
signal  spi_dout_1      : std_logic; -- spi 0 data output

signal  spi_clki_2      : std_logic; -- spi 0 clock input
signal  spi_stri_2      : std_logic; -- spi 0 strobe input
signal  spi_din_2       : std_logic; -- spi 0 data input
signal  spi_dout_2      : std_logic; -- spi 0 data output

signal  eth_switch_bus  : std_logic_vector( 23 downto 0);

signal  err_led_1       : std_logic; --
signal  err_led_2       : std_logic; --

signal  j2_spare        : std_logic_vector(5 downto 0);
signal  j4_spare        : std_logic_vector(8 downto 0);

signal valid            : std_logic_vector(2 downto 1) := "11";

signal  spi_clki_1m     : std_logic;
signal  spi_stri_1m     : std_logic;
signal  spi_din_1m      : std_logic;
signal  error_sclk1     : std_logic := '0';
signal  error_sstr1     : std_logic := '0';
signal  error_sdat1     : std_logic := '0';
signal  sclk_stuck1     : std_logic := '0';
signal  sstr_stuck1     : std_logic := '0';
signal  sdat_stuck1     : std_logic := '0';

signal  spi_clki_2m     : std_logic;
signal  spi_stri_2m     : std_logic;
signal  spi_din_2m      : std_logic;
signal  error_sclk2     : std_logic := '0';
signal  error_sstr2     : std_logic := '0';
signal  error_sdat2     : std_logic := '0';
signal  sclk_stuck2     : std_logic := '0';
signal  sstr_stuck2     : std_logic := '0';
signal  sdat_stuck2     : std_logic := '0';

signal  SW_UP           : std_logic;
signal  SW_DN           : std_logic;

signal Log0             : std_logic;

begin
    Log0 <= '0';
    -- turn manual control off
    SW_UP <= '1';
    SW_DN <= '1';

    -- crystal osc clock
    xclk_in <= not xclk_in after Td2;

    -- power up reset
    rst_n  <= '0' after 0 ns,
              '1' after 40*Td2;

    process(spi_stri_1)
    begin
        if falling_edge(spi_stri_1) then
            valid <= not(valid(1)) & valid(2);
        end if;
    end process;

spim1: spi_master_dcs
generic map(Td2 => 50 us,
            startpos => 0)
    port map(
        valid         => valid(1),
        spi_clko      => spi_clki_1m,
        spi_stro      => spi_stri_1m,
        spi_din       => spi_dout_1,
        spi_dout      => spi_din_1m);

        -- emulate bad data on channel 1
        spi_clki_1  <= (spi_clki_1m xor error_sclk1) or sclk_stuck1;
        spi_stri_1  <= (spi_stri_1m xor error_sstr1) or sstr_stuck1;
        spi_din_1   <= (spi_din_1m xor error_sdat1) or sdat_stuck1;

        process
        begin

            wait; -- turn off the errors
            wait until falling_edge(valid(2));
            wait until rising_edge(spi_clki_1m);
            wait for 30 us;
            error_sdat2 <= '1';
            wait for 250 us;
            error_sdat2 <= '0';
            wait for 250 us;
            sdat_stuck2 <= '1';
            wait for 500 us;
            sstr_stuck2 <= '1';
            wait for 250 us;
            sclk_stuck2 <= '1';
--        error_sstr <=
--        error_sdat <=
--            wait;

        end process;

spim2: spi_master
generic map(Td2 => 50 us,
            startpos => 1)
    port map(
--        valid         => valid(2),
        valid         => Log0,
        spi_clko      => spi_clki_2m,
        spi_stro      => spi_stri_2m,
        spi_din       => spi_dout_2,
        spi_dout      => spi_din_2m);

        -- emulate bad data on channel 2
        spi_clki_2  <= (spi_clki_2m xor error_sclk2) or sclk_stuck2;
        spi_stri_2  <= (spi_stri_2m xor error_sstr2) or sstr_stuck2;
        spi_din_2   <= (spi_din_2m xor error_sdat2) or sdat_stuck2;

dut: top
  port map
        (
        reset_n         => rst_n,
        xclk_in         => xclk_in,

        spi_clki_1      => spi_clki_1,
        spi_stri_1      => spi_stri_1,
        spi_din_1       => spi_din_1,
        spi_dout_1      => spi_dout_1,

        spi_clki_2      => spi_clki_2,
        spi_stri_2      => spi_stri_2,
        spi_din_2       => spi_din_2,
        spi_dout_2      => spi_dout_2,

        SW_UP           => SW_UP,
        SW_DN           => SW_DN,

        A_sel           => eth_switch_bus(11 downto  0),
        B_sel           => eth_switch_bus(23 downto 12),

        LED             => open,
        LED_jtag_const  => open,

        j2_spare        => j2_spare,
        j4_spare        => j4_spare);

end;