-- $Id$:

library ieee;
use ieee.std_logic_1164.all;

entity spi_master_dcs is
generic (Td2 : time := 50 us; -- for 10 kHz
         startpos : Natural := 1);
    port (
        valid         : in  std_logic; -- bit31
        spi_clko      : out std_logic; -- spi 0 clock input
        spi_stro      : out std_logic; -- spi 0 strobe input
        spi_din       : in  std_logic; -- spi 0 data input
        spi_dout      : out std_logic); -- spi 0 data output
end spi_master_dcs;

architecture sim of spi_master_dcs is

component hamming_enc is
    port (
          din   : in  std_logic_vector (31 downto 0);  -- data from the device
          dout  : out std_logic_vector (38 downto 0)   -- data to instr. memory
          );
end component;

component fdiv is

port(
    --clock input
    clk_in  : in std_logic;
    rst_n   : in std_logic;

    --clock output
    clk_out : out std_logic;
    pulse_out : out std_logic;
    en_out   : out std_logic
    );
end component;

component shreg_parin is
generic(N : Integer := 32);
port(
    --inputs
    rst_n    : in    std_logic;
    PARIN    : in    std_logic_vector(N downto 1);
    CLK      : in    std_logic;
    EN       : in    std_logic;
    --outputs
    SDOUT    : out   std_logic;
    SSTR     : out   std_logic;
    sclk     : out   std_logic
    );
end component;

component shreg is
generic(N : Integer := 24);
port(
    rst_n    : in    std_logic;
    SCLK     : in    std_logic;
    SDIN     : in    std_logic;
    SSTR     : in    std_logic;
    EN       : in    std_logic;
    SDOUT7s  : out   std_logic;
    SDOUT    : out   std_logic;
    PAROUTd  : out   std_logic_vector(N downto 1);
    PAROUT   : out   std_logic_vector(N downto 1)
    );
end component;

component hamming_dec

  port
        (
        din     : in  std_logic_vector (38 downto 0);  -- data input from spi deserialiser
        dout    : out std_logic_vector (31 downto 0);  -- data output
        state   : out std_logic_vector ( 1 downto 0)   -- error status 1..0
        );

end component;

signal fclk     : std_logic := '0';
signal sclk     : std_logic := '0';
signal rst_n    : std_logic := '0';
constant data_ini : std_logic_vector(31 downto 0) := (startpos => '1', others => '0');
signal data     : std_logic_vector(31 downto 0) := data_ini;
signal dback    : std_logic_vector(31 downto 0);
signal data_h   : std_logic_vector(38 downto 0);
signal PAROUT   : std_logic_vector(38 downto 0);
signal state_back : std_logic_vector(1 downto 0);
signal en_out   : std_logic;
signal spi_stro_i   : std_logic;

begin

    fclk <= not fclk after Td2/400;
    rst_n <= '0' after 0 ns,
             '1' after 2.5*Td2;


    process(valid)
    begin
        if valid='0' then
            data <= (others => '0');
        else
            data <= data_ini;
            data(data'high) <= valid;
        end if;
    end process;

henc: hamming_enc
    port map(
          din   => data,
          dout  => data_h);

fd: fdiv

port map(
    --clock input
    clk_in  => fclk,
    rst_n   => rst_n,

    --clock output
    clk_out => sclk,
    pulse_out => open,
    en_out   => en_out);

shparin: shreg_parin
generic map(N => 39)
port map(
    --inputs
    rst_n    => rst_n,
    PARIN    => data_h,
    CLK      => sclk,
    EN       => en_out,
    --outputs
    SDOUT    => spi_dout,
    SSTR     => spi_stro_i,
    sclk     => open
    );

    spi_stro <= spi_stro_i;

    spi_clko <= en_out;

serrecv: shreg
generic map(N => 39)
port map(
    rst_n    => rst_n,
    SCLK     => sclk,
    SDIN     => spi_din,
    SSTR     => spi_stro_i,
    EN       => en_out,
    SDOUT7s  => open,
    SDOUT    => open,
    PAROUTd  => open,
    PAROUT   => PAROUT);

hdec: hamming_dec

  port map
        (
        din     => PAROUT,
        dout    => dback,
        state   => state_back);

end;