-- $Id$:

library ieee;
use ieee.std_logic_1164.all;

entity spi_master is
generic (Td2 : time := 50 us;
         startpos : Natural := 1);
    port (
        spi_clko      : out std_logic; -- spi 0 clock input
        spi_stro      : out std_logic; -- spi 0 strobe input
        spi_din       : in  std_logic; -- spi 0 data input
        valid         : in  std_logic; -- bit31
        spi_dout      : out std_logic); -- spi 0 data output
end spi_master;

architecture sim of spi_master is

component hamming_enc is
    port (
          din   : in  std_logic_vector (31 downto 0);  -- data from the device
          dout  : out std_logic_vector (38 downto 0)   -- data to instr. memory
          );
end component;

signal sclk     : std_logic := '0';
signal data     : std_logic_vector(31 downto 0) := (startpos => '1', others => '0');
signal data_h   : std_logic_vector(38 downto 0);
signal data_hr  : std_logic_vector(data_h'range);
signal bitcnt   : Natural range 0 to 38 := 0;

begin

    sclk <= not sclk after Td2;
    data(data'high) <= valid;

henc: hamming_enc
    port map(
          din   => data,
          dout  => data_h);

    process(sclk)
    begin
        if falling_edge(sclk) then
            if bitcnt=0 then
                data_hr <= data_h;
                spi_stro <= '1';
                -- change the data
                --data <= data(data'high-1 downto 0) & data(data'high);
            else
                data_hr <= data_hr(data_hr'high-1 downto 0) & data_hr(data_hr'high);
                spi_stro <= '0';
            end if;
            if bitcnt < 38 then
                bitcnt <= bitcnt + 1;
            else
                bitcnt <= 0;
            end if;
        end if;
    end process;

    spi_dout <= data_hr(data_hr'high) after 5 ns;
    spi_clko <= sclk;

end;