// $Id: run_parameters.tcs 5885 2021-02-07 16:54:21Z angelov $: // asm NAME=VALUE constants that will be used in the assembler and in the .tcs files // const NAME=VALUE constants that will be used only in the .tcs files // note that more than 30 samples can not be sent in a black event! // the normal readout is for Nsamples up to 30. It must be multiple of 3, or the last word sent will have invalid fields. // the case Nsamples > 30 works only in ZS mode with an additional time compression - the transfer starts not from timebin 0, but // later, 2 samples before the first "non-zero" sample. asm NSAMPLES = {{ timebins }}; // e.g. 18, 21, 24, 27, 30 (max) OR in time compression mode 33..63 (max) restrict NSAMPLES>30 // in this case one must specify the number of 32-bit words used to transfer one channel. // 3*NWORDS-1 ADC samples will be transferred, instead of the first sample // size << 6 | time_offset will be send. Here size is NWORDS (1..10), offset is the first sample# transferred, 0..60 asm NWORDS = 7; // used only when NSAMPLES > 30?, 10 is the max asm NBEG_PRE =5; // number of presamples in ZS with >30 samples restrict 1 // when defined, at this event the full configuration will be sent // when not desired - don't define it at all! asm ConfigEvent = 1; // ----------------------------------------- // Parts of the configuration register SMMODE // global timing parameters // ----------------------------------------- const smmode_delta = 6; // 4 bit, window for L0A, L1A const smmode_eod2cpu = 8; // 5 bit, end of drift time to CPU on delay const smmode_simflag = 0; // 1 bit, simulation flag used to replay the ADC data from EB // Parts of the configuration register SM0..2 restrict SIMULATION==0 const ignore_L0R = 0; const ignore_L1R = 0; const LTIME0 = 0x0090; // 14-bit, used for L0A/R const LTIME2 = 0x03a8; // 14-bit, used for L1A/R const LTIME1 = 0x0390; // 14-bit, used to start the raw data readout, a little bit later const adc_az_pretr_sim = 0; // bit 8 in ADCPAR must be set for VHDL simulation! Clear for normal operation restrict SIMULATION==1 // HDL simulation case const ignore_L0R = 1; const ignore_L1R = 1; const LTIME0 = 48; // 14-bit, used for L0A/R const LTIME2 = 0x03a8; // 14-bit, used for L1A/R const LTIME1 = 0x0390; // 14-bit, used to start the raw data readout, a little bit later const adc_az_pretr_sim = 1; // bit 8 in ADCPAR must be set for VHDL simulation! Clear for normal operation restrict 1 // ----------------------------------------- // Fitprogram mode // ----------------------------------------- // possible values: // TRACKLETS_3Q_MODE - new tracklet mode with 3 charge integration windows // TRACKLETS_DIS_MODE - sending of tracklets disabled, effectively the TRAPs run in test pattern mode (tracklets) without processing the fit register // TRACKLETS_TPT_MODE - generate test pattern tracklets // TRACKLETS_COS_MODE - cosmic mode for tracklets asm TRACKLETS_MODE = TRACKLETS_3Q_MODE; // add 0x80 to the HCID in the HCM header for tracklets? // this should be fixed later and dissappear as option //asm ADD_CONST_TO_HCID = 0x80 // either 0 or not defined, OR 0x80 restrict TRACKLETS_MODE != TRACKLETS_COS_MODE // in _DIS_, _3Q_, _TPT_ mode: send MCM headers when no tracklets found? asm DONT_SEND_EMPTY_HDR_TR = 1; // additional parameters in case of Cosmic Mode restrict TRACKLETS_MODE == TRACKLETS_COS_MODE // for cosmic trigger: set the thresholds: asm COSMIC_MIN_HITS = 4; // min number of hits, 5 bit asm COSMIC_Q_THR = 350; // threshold for the total cluster charge/MCM, 16 bit //NOT USED any more! asm COSMIC_Q_SHR = 4; // shift right the total cluster charge/MCM, 3 bit restrict TRACKLETS_MODE == TRACKLETS_3Q_MODE // 1 - use floating point representation of the charges? // 0 - otherwise scaling by a fixed factor asm DYN_FP_Q = 1; // floating point mode for Q enabled asm TR_ADCMSK_AND = 0; // 0 or 1, enable to AND the ADCMSK with the tracklet contributing channel mask // test pattern only restrict TRACKLETS_MODE == TRACKLETS_TPT_MODE // probabilities for 1, 2, 3 tracklets/MCM in parts per 1000, in order to avoid using floating point numbers const TEST_PAT_1_TR = 500; // 50 for 5 % const TEST_PAT_2_TR = 200; // 20 for 2 % const TEST_PAT_3_TR = 100; // 10 for 1 % // cramble word, lower und upper 16-bits asm SCRM_WORD_L = 0xFACE; asm SCRM_WORD_H = 0xDEAD; restrict 1; // select the raw data readout mode, one of: // RAW_RDOUT_FULL - full readout, all ADC channels // RAW_RDOUT_ZS - zero suppressed readout, selected ADC channels completely (NSAMPLES up to 30) or // selected ADC channels in a time slice (NSAMPLES > 30) // RAW_RDOUT_TP - test pattern, more like full readout asm RAW_RDOUT_MODE = RAW_RDOUT_FULL; // Options available only in case of full readout restrict RAW_RDOUT_MODE==RAW_RDOUT_FULL; WITH_STAT = 1; // 1 or 0 - with accumulating RMS statistics or not (default=0) WITH_FIT2DM = 1; // 1 or 0 - store the fit registers in DMEM for debugging (default=0) // Options available only in case of ZS restrict RAW_RDOUT_MODE==RAW_RDOUT_ZS; // select raw data readout mode // possible values: ZS_FULL_NO, ZS_FULL_1, ZS_FULL_2, ZS_FULL_3 // ZS_FULL_NO - always send zero suppressed ADC data // ZS_FULL_1 - each 128 (ZS_FULL_N1) \ // ZS_FULL_2 - each 256 (ZS_FULL_N2) - events send all ADC channels // ZS_FULL_3 - each 1024 (ZS_FULL_N3) / // Note: ZS_FULL_N1/2/3 are defined in run_pre_const.tcs and are 2**N-1 asm ZS_FULL_MOD = ZS_FULL_NO; asm DONT_SEND_EMPTY_HDR_ZS = 0; // 0 or 1, suppress sending MCM header when no ADC data // select one of: ZS_TRACKL_DIS_CONTR, ZS_TRACKL_ENA_CONTR, ZS_TRACKL_CND_CONTR: // - disable any contribution from channels with tracklets/candidates // - enable contribution from channels with tracklets // - enable contribution from channels with tracklet candidates (this condition is weaker!) asm ZS_TRACKL=ZS_TRACKL_CND_CONTR; // enable AND of the selected ADC channels with the value of ADCMASK register asm ZS_ADCMSK_AND =1; // 0 or 1, will be shifted to bit 2 of min_ver // enable OR of the selected ADC channels with a special mask stored in DMEM in ZS_ADC_ORM_DM asm ZS_ADCMSK_OR =1; // if 1, ZS_ADC_OR_Mask must be set and stored in DMEM in ZS_ADC_ORM_DM_SCSN // default is 0 in this case, as may be it will be non-zero only at some single // MCMs and set later by the patch-maker const ZS_ADC_OR_Mask = 0x0; // send some ADC channels always, this parameters is locally different // may be count to the patch maker? // TP related options restrict RAW_RDOUT_MODE==RAW_RDOUT_TP; RAW_TP_TYPE = 0; // test pattern type, from 0 to 7 of them // 1, 2, 3, 6 - recommended, // 0 - still possible, // 4, 5, 7 - not implemented! restrict 1; // For debugging only, store ADC data in DMEM for SCSN readout: // possible values: // RAW_SCSN_ALL - store all ADC channels in DMEM, can be combined with any RAW_RDOUT_MODE // (this costs more CPU time/power in ZS mode) // RAW_SCSN_ZS - store only the selected ADC channels in DMEM, available only in RAW_RDOUT_ZS // (almost no additional CPU time/power compared to the last option) // RAW_SCSN_DIS - disable storing ADC data in DMEM asm RAW_SCSN = RAW_SCSN_DIS; // ----------------------------------------- // Fit parameters // ----------------------------------------- // in _3Q_: // - parameters of the 3-rd charge window Q2: left margin and width asm Q2_LEFT_MRG_VAL = 7; asm Q2_WIN_WIDTH_VAL = 7; // ----------------------------------------- // ADC, eventually could be modified // ----------------------------------------- restrict SIMULATION==0 const ADCdatapipe = 5; // from 0 to 5, 2 clocks already lost in the Crosstalk filter, copied to EBD_VAL restrict SIMULATION==1 const ADCdatapipe = 0; // from 0 to 5, 2 clocks already lost in the Crosstalk filter, copied to EBD_VAL restrict 1 const ADCraw = 0; // 0 - store filtered, 1 - store raw ADC data in the event buffers, copied to EBSF_VAL // ADCPAR fields: IRQ, sampling phase, en inp buffer, autozero, power const adc_power_backgr = 5; // 0..7 = p const adc_power_pretr = 5; // 0..7 = h const adc_irq_phase = 6; // 0..11 = i const adc_smp_phase = 2; // 0..11 = s const adc_enibf_backgr = 0; // 0 or 1 = e const adc_enibf_pretr = 0; // 0 or 1 = b const adc_az_backgr = 0; // 0 or 1 = a const adc_az_pretr = 0; // 0 or 1 = z asm ADCDAC_VAL = 00000b; // 5 bit // This is eventually a patch maker or calibration parameter // ----------------------------------------- // Preprocessor parameters // ----------------------------------------- asm TPFS_VAL = 5; // fit start asm TPFE_VAL = 24; // fit end asm TPQS0_VAL = 0; // first Q window start asm TPQE0_VAL = 6; // first Q window end asm TPQS1_VAL = 14; // second Q window start asm TPQE1_VAL = 20; // second Q window end asm TPFP_VAL = 40; // Filtered Pedestal, with 2 additional bits (x4) asm TPHT_VAL = 200; // Cluster Charge Threshold asm TPVT_VAL = 0; // Cluster Quality threshold asm TPVBY_VAL = 0; // Cluster Verification Bypass asm TPCT_VAL = 8; // Tracklet Candidate Total Hit Number Threshold asm TPCL_VAL = 2; // Tracklet Candidate Left Hit Number Threshold asm TPCBY_VAL = 1; // Test Indices Flag, 0 for bypass the tracklet candidate selection, controlled by the assembler program asm TPD_RST_VAL = 15; // the reset value, but need to be refreshed // ----------------------------------------- // Fit program parameters // ----------------------------------------- restrict TRACKLETS_MODE != TRACKLETS_TPT_MODE asm INV_FIT_POS = 1; // change the numbering direction, when 1, the calculated position will be inverted // pos = pos - offs_y (when 0) or pos = offs_y - pos (when 1) const SCALE_Y = 0x28000000; // 80 steps/pad => 8/256*2**32 const SCALE_D = 0x7FFFFFFF; // 1/2 *0xFFFFFFFF // the offset must be in the same units as used in the tracklet calculation BEFORE multiplying to SCALE_Y! // therefore : we have 2**PAD_EXT steps in one pad, here the middle of the chip const OFFS_Y = (21 << PAD_EXT)/2; // the center of the chip with the additional bits restrict 1 const SCALE_Q = 0x10000000; const DEFL_CR = 0x00045678; // ----------------------------------------- // Filter parameters // ----------------------------------------- // 1/0 enable/disable the corresponding filter or correction // in case of SIMULATION the filters are bypassed in the post.tcs const EnableNonlinearity = 0; const EnablePedestal = 1; const EnableGainCorrection = 1; const EnableTailCancellation = 1; const EnableXtalkSuppression = 0; // ----------------------------------------- // Pedestal filter parameters // ----------------------------------------- const PedestalTimeConstant = 0; // 0 for fastest, 3 for slowest const EffectPedestal = 10; //const FPNPvalue = 32; // with two additional bits, divide by 4 in order to get the input ADC units // The baseline at the output of the pedestal filter is still not the final! // Set the baseline variation parameters in FPNPvalue and GainPedestalIni: //const FPNPvalue=4*(EffectPedestal+1/2)*(1+EnableTailCancellation*(-1+45/14))*XtalkF0*(9-EnableGainCorrection)/9; // FPNP is restricted to 0 ... 127.75 (7+2 bits) // ----------------------------------------- // Tail cancellation filter parameters // ----------------------------------------- const LongDecayWeight = 200; const LongDecayParameter = 200; const ShortDecayParameter = 0; // Xtalk is disabled // Crosstalk Filter Parameters const XtalkM0=0x1E * EnableXtalkSuppression; // not expected to be used actually const XtalkM1=0xD4 * EnableXtalkSuppression; // not expected to be used actually const XtalkM2=0xE6 * EnableXtalkSuppression; // not expected to be used actually const XtalkM3=0x4A * EnableXtalkSuppression; // not expected to be used actually const XtalkM4=0xEF * EnableXtalkSuppression; // not expected to be used actually const XtalkF0=1; // This is correct only when Xtalk disabled! // Otherwise, the DC responce of the filter must be calculated // ----------------------------------------- // Zero suppression // ----------------------------------------- const EBSingleIndicatorThreshold = 16; // EBIS const EBSumIndicatorThreshold = 1; // EBIT => not used when we care only about single indicator threshold (LUT=0x0F) // EBIL Table: mark pad if one of the conditions is true: // 0: hit >= 16 && cluster >= 1 && local max // 1: hit >= 16 && cluster >= 1 && not local max // 2: hit >= 16 && cluster < 1 && local max // 3: hit >= 16 && cluster < 1 && not local max // 4..7 hit < 16, the same other combinations // explained // bit 0=0: the channel is a local max, >= than the neighbours // bit 1=0: the sum over the channel-1, channel, channel+1 is over the threshold EBIT // bit 2=0: the channels is above the threshold EBIS // the 3 bits form a number from 0 to 7, the corresponding bit in EBIL // if we want to use the single threshold, then bi 2 must be 0 - all bit positions 0..3 of EBIL must be 1 if we use positive logic // in the indicators: 0000 1111. In this case we don't care about the other two conditions and EBIT is don't care const EBIndicatorLookupTable = 0x0F; // EBIL const EBmarkIgnoreNeighbour = 1; //EBIN // these two parameters will be additionally AND-ed with a mask = (1 << NSAMPLES) - 1 EBmask_32_63 = 0xFFFFFFFF; // stored in DMEM in ZS_SMSK... EBmask_0_31 = 0xFFFFFFFF;