// scsn_ids.tcs
//
// Jan.03,2006 KO added setup for 3B
// Feb.02,2006 KO modified to have ALICE numbering (use ROB_ALICE=1)

ROB_1A=0;
ROB_1B=0;
ROB_2B=0;
ROB_3A=0;
ROB_3B=0;
ROB_4A=0;
ROB_4B=0;
MCM   =0;
WAFER =0;
SIMULATION=0;
FULLROB=0;
SINGLEROB=0;
ROB_ALICE = 0;

// Modify only this part !!!

SIMULATION= 0;
FULLROB   = 1;
// This must be 0 for chamber, 1 for single ROB operation.
SINGLEROB = 0;
ROB_3B    = 0;
// Default is ALICE numbering output
ROB_ALICE = 1;

// select the hamming correction on/off
HAMMIM=0;
HAMMDM=0;
HAMMDB=0;

// end of modify

// ----------------------------------------------------------
//  define SCSN IDs for ring 0 (ALICE numbering v.s. SCSN ID)
// ----------------------------------------------------------
ROB   = ROB_1A | ROB_1B | ROB_2B | ROB_3A | ROB_3B | ROB_4A | ROB_4B | ROB_ALICE

restrict ROB

// Here is special chip group expanded by control engine on DCS.

// 11 = 4+7 bits
// 4 bits: for ROB  selection
// 7 bits: for Chip selection

const chip_cmrg   = 00001000001b; // All Column Merger chips (ALICE#2,6,10,14)
const chip_bmrg   = 00001000010b; // All board merger chips (ALICE#16)
const chip_hm3    = 00001000100b; // Half chamber merger on C0 chamber
const chip_hm4    = 00001001000b; // Half chamber merger on C1 chamber
const chip_edge   = 00001010000b; // All MCM's at the edge of CHAMBER (depends on side)
const chip_norm   = 00001100000b; // All ADC chips except for edge , colmrg
const chip_all    = 00001111111b; // Same as 127, this is special

// ROB Selections
const chip_rob0   = 10000000000b; // Restrict to chips in ROB position 0   T1A
const chip_rob1   = 10010000000b; // Restrict to chips in ROB position 1   T1B
const chip_rob2   = 10100000000b; // Restrict to chips in ROB position 2   T1A
const chip_rob3   = 10110000000b; // Restrict to chips in ROB position 3   T2B
const chip_rob4   = 11000000000b; // Restrict to chips in ROB position 4   T3A
const chip_rob5   = 11010000000b; // Restrict to chips in ROB position 5   T3B
const chip_rob6   = 11100000000b; // Restrict to chips in ROB position 6   T4A
const chip_rob7   = 11110000000b; // Restrict to chips in ROB position 7   T4B
const chip_a_side = 00010000000b; // Restrict to chips in all ROBs in A side (pos0,2,4,6)
const chip_b_side = 00100000000b; // Restrict to chips in all ROBs in B side (pos1,3,5,7)
const chip_t3ab   = 01000000000b; // Restrict to chips in only T3A and T3B (where ORI is)
const chip_allrob = 00000000000b; // Do not restrict.

restrict ROB_ALICE

// It is Alice numbering definition
const chip0  =    0;
const chip1  =    1;
const chip2  =    2; // merger
const chip3  =    3;
const chip4  =    4;
const chip5  =    5;
const chip6  =    6; // merger
const chip7  =    7;
const chip8  =    8;
const chip9  =    9;
const chip10 =   10; // merger
const chip11 =   11;
const chip12 =   12;
const chip13 =   13;
const chip14 =   14; // merger
const chip15 =   15;
const chip_bm =  16; // board merger
const chip_hm =  17; // half chamber merger

restrict ROB_1A | ROB_4A
const chip0  =  10;
const chip1  =  11;
const chip2  =  12; // merger
const chip3  =  13;
const chip4  =  09;
const chip5  =  16;
const chip6  =  15; // merger
const chip7  =  14;
const chip8  =  08;
const chip9  =  06;
const chip10 =  07; // merger
const chip11 =  01;
const chip12 =  05;
const chip13 =  04;
const chip14 =  03; // merger
const chip15 =  02;
const chip_bm = 17;

restrict ROB_1B | ROB_2B | ROB_4B
const chip0  =  11;
const chip1  =  12;
const chip2  =  13; // merger
const chip3  =  14;
const chip4  =  10;
const chip5  =  17;
const chip6  =  16; // merger
const chip7  =  15;
const chip8  =  09;
const chip9  =  07;
const chip10 =  08; // merger
const chip11 =  02;
const chip12 =  06;
const chip13 =  05;
const chip14 =  04; // merger
const chip15 =  03;
const chip_bm = 01;

restrict ROB_3A
const chip0  =  10;
const chip1  =  11;
const chip2  =  12; // merger
const chip3  =  13;
const chip4  =  09;
const chip5  =  16;
const chip6  =  15; // merger
const chip7  =  14;
const chip8  =  08;
const chip9  =  06;
const chip10 =  07; // merger
const chip11 =  01;
const chip12 =  05;
const chip13 =  04;
const chip14 =  03; // merger
const chip15 =  02;
const chip_bm = 18; // board merger
const chip_hm = 17; // half chamber merger

restrict ROB_3B
const chip0  =  12;
const chip1  =  13;
const chip2  =  14; // merger
const chip3  =  15;
const chip4  =  11;
const chip5  =  18;
const chip6  =  17; // merger
const chip7  =  16;
const chip8  =  10;
const chip9  =  08;
const chip10 =  09; // merger
const chip11 =  03;
const chip12 =  07;
const chip13 =  06;
const chip14 =  05; // merger
const chip15 =  04;
const chip_bm = 02; // board merger
const chip_hm = 01; // half chamber merger

restrict ROB

const  type=1; // if 0 - for single chip

// 1 for single chip, 2 for the new MCM tester, 127 for the ROB
//const dut = 127;
const scheck = 2;

restrict ROB_3A | ROB_3B
const chip_mode  = chip15; // for ROB =1, for single chip is jumper
const chip_jtag  = chip7;  // for ROB=13, for single chip = 1

restrict ROB_ALICE
const chip_mode  = chip15 | chip_t3ab;
const chip_jtag  = chip7  | chip_t3ab;
const dutOri = chip_hm | chip_t3ab;

restrict 1 - (ROB_3A | ROB_3B | ROB_ALICE )
const chip_mode  = 99; // not present
const chip_jtag  = 99; // not present

restrict MCM

// 1 for ROB, 0 for single chip of GIOtst
const type = 0;

// 1 for single chip, 2 for the new MCM tester, 3 for the wafer tester, 127 for the ROB
const fpga2 = 1;
const fpga1 = 2;
const dut = 2;
const ni0 = 3;
const ni1 = 4;
const ni2 = 5;
const ni3 = 6;
const scheck =2;

restrict WAFER
// 1 for ROB, 0 for single chip of GIOtst
const type = 0;

// 1 for single chip, 2 for the new MCM tester, 3 for the wafer tester, 127 for the ROB
const fpga2 = 1;
const fpga1 = 2;
const dut = 3;
const scheck = 3;

restrict 1

USE_J2C = 1;