/**************************************/ /* ALICE TRD */ /* Read-out board */ /* SCSN Configuration File */ /* */ /* 2004-03-08 */ /* Jan de Cuveland, Venelin Angelov */ /**************************************/ // ------------------------- // set int entry addresses // ------------------------- include src/ori/fitprog.cpu0.labels.tcs include src/ori/fitprog.cpu1.labels.tcs include src/ori/fitprog.cpu2.labels.tcs include src/ori/fitprog.cpu3.labels.tcs write IA0+irq_tst, lbl_LPW_cpu0; // set int_clr start addr for cpu0 write IA1+irq_tst, lbl_LPW_cpu1; // set int_clr start addr for cpu0 write IA2+irq_tst, lbl_LPW_cpu2; // set int_clr start addr for cpu0 write IA3+irq_tst, lbl_LPW_cpu3; // set int_clr start addr for cpu0 write IA0+irq_clr, lbl_CLR_cpu0; // set int_clr start addr for cpu0 write IA1+irq_clr, lbl_CLR_cpu1; // set int_clr start addr for cpu1 write IA2+irq_clr, lbl_CLR_cpu2; // set int_clr start addr for cpu2 write IA3+irq_clr, lbl_CLR_cpu3; // set int_clr start addr for cpu3 write IA0+irq_acq, lbl_ACQ_cpu0; // set int_acq start addr for cpu0 write IA1+irq_acq, lbl_ACQ_cpu1; // set int_acq start addr for cpu1 write IA2+irq_acq, lbl_ACQ_cpu2; // set int_acq start addr for cpu2 write IA3+irq_acq, lbl_ACQ_cpu3; // set int_acq start addr for cpu3 write IA0+irq_raw, lbl_RAW_cpu0; // set int_raw start addr for cpu0 write IA1+irq_raw, lbl_RAW_cpu1; // set int_raw start addr for cpu1 write IA2+irq_raw, lbl_RAW_cpu2; // set int_raw start addr for cpu2 write IA3+irq_raw, lbl_RAW_cpu3; // set int_raw start addr for cpu3 // --------------- // set int masks // --------------- const irq_msk = (1 << irq_acq) | (1 << irq_clr) | (1 << irq_raw) | (1 << irq_tst); write IRQHW0, irq_msk; // set irq_hw mask for cpu0 write IRQHL0, irq_msk; // set irq_hl mask cor cpu0 write IRQHW1, irq_msk; // set irq_hw mask for cpu1 write IRQHL1, irq_msk; // set irq_hl mask cor cpu1 write IRQHW2, irq_msk; // set irq_hw mask for cpu2 write IRQHL2, irq_msk; // set irq_hl mask cor cpu2 write IRQHW3, irq_msk; // set irq_hw mask for cpu3 write IRQHL3, irq_msk; // set irq_hl mask cor cpu3 // ------------------------- // configure clock control // ------------------------- write CPU0CLK, 0x3F; write CPU1CLK, 0x3F; write CPU2CLK, 0x3F; write CPU3CLK, 0x3F; // ----------------------------- // configure network interface // ----------------------------- // output delays optimized for the FPGA write NED,(root_flag << 14) | (oase_mode << 15) | (t_parit_bit1 << 10) | (t_false_bit1 << 6) | (t_ctrl_delay << 3) | t_strb_delay; write NDLY, (t_data_delay0) | (t_data_delay1 << 3) | (t_data_delay2 << 6) | (t_data_delay3 << 9) | (t_data_delay4 << 12) | (t_data_delay5 << 15) | (t_data_delay6 << 18) | (t_data_delay7 << 21) | (t_data_delay8 << 24) | (t_data_delay9 << 27); // readout order configuration constants const niro_dut = 0x0003fffc; // own data only // set NI tracklet readout order write dutOri, NTRO, niro_dut; // set NI raw data readout order write dutOri, NRRO, niro_dut; // set end signature (rr: 0x----0000, tr: 0x----1000) write NES, nsig_tr | (nsig_rr << 16); // timers for NI signals write dutOri, NITM0, 0x01D0; // 0x153; // NI timer 0 (clock) write dutOri, NITM1, 0x01E2; // 0x165; // NI timer 1 (IO data) write dutOri, NITM2, 0x022F+24+100; // NI timer 2 (clock) write dutOri, NIP4D, 0xFF; // delays // configuration of the NI clock write dutOri, NICLK, 0x3F; // configuration of the NI output data port //write dutOri, NIODE, 1; //00010b; // configuration of the NI output control port write dutOri, NIOCE, 0x01; // was 3 // was 7 // configuration of the NI input data ports write NIIDE, 0x3F; // configuration of the NI input control ports write NIICE, 0x3F; // --------------------- // misc. configuration // --------------------- // ADC off // mask the ADCs with open inputs, first mask all write dutOri, ADCMSK, 0x0 // Drift time write dutOri, TPPT0, 0x0D; // skip first 10 samples write dutOri, TPPAE, 0x15; // acquire 21 samples write dutOri, TPPGR, 0x14; // start CPUs after 20 samples // -------------------------------- // configure global state machine // -------------------------------- write SML0, L0time; // consider L0 & L0_time = 0x050 (80) write SML1, L1time; // consider L1 & L1_time = 0x200 (512) write SML2, L2time; // consider L2 & L2_time = 0x2BC (700) // -------------------------------- // Assembler program parameters // -------------------------------- // ------------------------ // set constant registers // ------------------------ // c15 write dutOri, 0x0C07, nsig_rr // c12 write dutOri, 0x0C04, nwords; // c13, what to send in tracklet mode write dutOri, 0x0C05, 0xFB04C040; // c14, the mode word of the psr_counter write dutOri, 0xC06, 000000101111b | (cnt_mode << 9); // init the PSRG counters // c8 write dutOri, 0x0C00, 0xABCD8100 & simple_test_n;// write dutOri, 0x0C08, 0x12348200 & simple_test_n;// write dutOri, 0x0C10, 0x56788300 & simple_test_n;// write dutOri, 0x0C18, 0x9ABC8400 & simple_test_n;// // start values of the data-counters //write dutOri, 0x0C00, 0x00 //write dutOri, 0x0C08, 0x40 //write dutOri, 0x0C10, 0x80 //write dutOri, 0x0C18, 0xC0 // C10 write dutOri, 0x0C02, nsig_tr write dutOri, 0x0C0A, nsig_tr write dutOri, 0x0C12, nsig_tr write dutOri, 0x0C1A, nsig_tr // c9 of cpu0 contains the number of packets sent // write dutOri, 0x0C01, 0;