#inc ; ------------------------------------------------------------------ ; -- -- ; -- Test program for the readout board -- ; -- For the ALICE TR-Detector at LHC -- ; -- Kirchhoff Institut für Physik -- ; -- Univesity of Heidelberg -- ; -- Germany -- ; -- -- ; -- 03.09.2004 VA -- ; ------------------------------------------------------------------ ; ;#def ByteMode=1 #def fullprog=1 #def srv_command = 0xF0E0 #def srv_indata = 0xF0E1 #def srv_outdata = 0xF0F0 ; number of words to send #def nsamples =c12 ; the configuration reg of the psr_counter #def psr_mode =c14 ; start value for the data generation #def psrg_ini =c8; #def endsig_rr= c15 ; end signature for raw data readout #def endsig_tr= c10 ; end signature for tracklet data readout #ifdef cpu0 #def clk_onoff = CPU0SS; #def psr_ini_gio = 0x0C00; #endif #ifdef cpu1 #def clk_onoff = CPU1SS; #def psr_ini_gio = 0x0C08; #endif #ifdef cpu2 #def clk_onoff = CPU2SS; #def psr_ini_gio = 0x0C10; #endif #ifdef cpu3 #def clk_onoff = CPU3SS; #def psr_ini_gio = 0x0C18; #endif ORG 0x0 lpw: nop nop nop ; low power mov 0, r0 sgio r0, clk_onoff jmpr cc_uncond, 0 nop #ifdef fullprog ; IRQ clr ORG 0x100; clr: nop #ifdef cpu0 mov cmd_ext_clr r0 mov c9 r5 or r5, r5, r5 jmp cc_zero clr_wt sub r5 c1 r5 sgio r5 0xC01 jmpr cc_busy 0 or r5, r5, r5 jmp cc_zero clr_wt sgio r0 SMCMD ; clear ready mov cmd_pretrigg r0 nop sgio r0 SMCMD #endif #ifdef cpu2 mov b1111_0101_0000, r1 jmpr cc_busy, 0 ; sgio r1, SMOFF ; switch off all NI LVDS cells, clk_prepr, clk_ni #endif clr_wt: jmpr cc_uncond, 0 nop ORG 0x200; acq: nop shl 8, c5, r8 add r8, c13, r8 ; -- some delay mov 31, r0 acq_delay: sub r0, c1, r0 jmp cc_nzero, acq_delay mov c10 r0 shl 8, r0, r0 shl 8, r0, r0 add r0, c10, r0 ; or r0, r8, r0 ; start address in GIO of the DBANK iext 0xF000 mov 0xF000, r14 add r14, c5, r14 ; start address in DMEM shl 2, c5, r15 ;acq_send: spio r0 NODP ; then send to the NI #ifdef cpu0 sgio+ r0 ; store to DBANK sra+ r0 ; store to DMEM #endif #ifdef cpu1 sgio+ r0 ; store to DBANK sra+ r0 ; store to DMEM #endif jmpr cc_uncond 0 nop ORG 0x400 raw: nop ; IRQ raw data read #ifdef cpu0 mov cmd_CPU_done r0 sgio r0 SMCMD; #endif ; start address in GIO of DBANK mov nsamples, r1 mul32 r1, c5, r1 iext 0xF002 mov 0xF002, r14 add r14, r1, r14 #ifdef ByteMode mov 0x0FF, r3; mask #else iext 0xFFFF; mov 0xFFFF, r3; mask #endif ; start address in DMEM mov 8, r15 shl 2, r1, r1 add r1, r15, r15 mov 0, r4; number of words mov nsamples, r9 ; configure the psr_counter mov psr_mode, r1 spio r1, 0x201; mov psrg_ini, r1 andt r1, r3 #ifndef ByteMode jmp cc_zero, raw_smp_test #endif spio r1, 0x200; initial data nop raw_wfull: #ifdef ByteMode and r1, r3, r1; bits 7..0 mov r1, r2 add r1, c1, r1 and r1, r3, r1; bits 7..0 shl 8, r1, r5 or r5, r2, r2; bits 15..8 add r1, c1, r1 and r1, r3, r1; bits 7..0 shl 8, r1, r5 shl 8, r5, r5 or r5, r2, r2; bits 23..16 add r1, c1, r1 and r1, r3, r1; bits 7..0 shl 8, r1, r5 shl 8, r5, r5 shl 8, r5, r5 or r5, r2, r2; bits 31..24 add r1, c1, r1 #else lpio 0x202, r1; read from PSRG and r1, r3, r1; take only bits 0..15 nop lpio 0x202, r2; read from PSRG shl 8, r2, r2; shift to 16..31 shl 8, r2, r2 or r2, r1, r2; merge with bits 16..31 #endif spio r2, NODP; store to NI sgio+ r2; store to DBANK sra+ r2; store to DMEM add r4, c1, r4; inc the number of words ; !!! In some TRAPs we have timing problems with the compare !!! ; Therefore here is double cmp r4, nsamples; check if ready cmp r4, r9 ; check if ready jmp cc_ltu, raw_wfull ; store the next word as start for the next pretrigger lpio 0x202, r2 jmpr cc_busy, 0 sgio r2, psr_ini_gio jmp cc_uncond, raw_sendem raw_smp_test: shl -1, r9, r8; the half of the data words to be send shl -8 r1, r1 shl -8 r1, r2 swp r2, r1 or r2, r1, r1 raw_wfulls: spio r1, NODP; store to NI sgio+ r1; store to DBANK sra+ r1; store to DMEM add r4, c1, r4; inc the number of words cmp r4, r8 jmpr cc_nzero, +2 not r1, r1 cmp r4, r9 jmp cc_ltu, raw_wfulls ; send end mark raw_sendem: mov endsig_rr, r0 spio r0, NODP #ifdef cpu3 ; only cpu3 to get the end marker at the end! jmpr cc_busy, 0 sgio+ r0; store to DBANK sra+ r0; store to DMEM jmpr cc_busy, 0 sgio+ r0; store to DBANK sra+ r0; store to DMEM #endif jmpr cc_busy, 0 ; switch power off mov 0, r0 sgio r0 clk_onoff ; each cpu stops its clock jmpr cc_uncond 0 nop #else clr: nop acq: nop raw: nop jmpr cc_uncond, 0 #endif ORG 0x700 ; Style recommendations ; ; 1) use include for the different parts of the CPU program ; ; 2) use prefix in the labels, e.g. ; ; -- start of the acq subroutine ; acq: ... ; ... ; acq_store: ; ... ; acq_delay: ; ... ; -- end of the acq subroutine ; ADDITIONAL PROGRAMS ; ; GENERAL RULES ; ; 1) The programs do not use any programmable constants ; 2) CPU3 is never used ; 3) The programs use for data exchange a small region in the DBANK ; or DMEM or IMEM3, accessible through GIO. The start addresses ; must be defined in the main program as follows: ; ; srv_command - command from the SCSN master, code of the service operation ; srv_indata - input data, stored by the SCSN master ; srv_outdata - output data, stored by the TRAP CPU ; ; 4) The programs may modify all registers (privat and global) ; ; 5) The programs end with command low power to the global state machine. ; This can be changed later - may be is reasonable to have the option for normal ; IRT (interrupt return) or just jump to some address. ; ; 6) By default the configuration of the main program enables interrupt TST for CPU0,1,2 ; but sets the start address to a small assembler code to switch the power off ; ; 7) When the SCSN master wants to start some service program, it must send the ; TRAP to the low power state, then modify the IVT (interrupt vector table) ; - store the correct start address of the service program. Then the SCSN master ; stores its request at srv_command and activates IRQ TST. The SCSN master checks ; the state of the TRAP and sends it to low power state if a timeout occurs. ; After finishing the service operation (which can consist of many service requests), ; the SCSN master restores the IVT to the original. ; J2C #ifdef cpu0 #inc "j2c.asm" #endif #ifdef cpu1 #inc "I2C.asm" #endif #ifdef cpu2 ;#inc "jtag.asm" tst: nop #endif