//include src/ori/chip_def.tcs
include src/ori/cpu0_labels.tcs

write dutOri, SMCMD, CMD_ACQ
expect dutOri, SMCMD, 0x30000220

//write dutOri, 0x0C00, 0xABCD8100 & simple_test_n;//
//write dutOri, 0x0C08, 0x12348200 & simple_test_n;//
//write dutOri, 0x0C10, 0x56788300 & simple_test_n;//
//write dutOri, 0x0C18, 0x9ABC8400 & simple_test_n;//

restrict WAFER
// WAFER TESTER ONLY
// clear the ni-input in FPGA
write   fpga1, 0x6002, 0
// number of words
expect  fpga1, 0x6002, 0
// number of parity errors
expect  fpga1, 0x6003, 0
// END WAFER TESTER ONLY

restrict 1
write dutOri, 0xC01, npackets
// c12
write dutOri,    0x0C04, nwords;
// pretrigger
write dutOri, SMCMD, CMD_PRETRIGG
//pretrigger 1
restrict USE_J2C

const   nw16 = npackets*2*(nwords*4+2+2);

wait 20000;

expect dutOri, SMCMD, 0x30000220
write SMCMD, CMD_LP;     // low power
expect 127, SMCMD, lp_state

write chip_mode, SEBDOU, mode_jtag;
write chip_mode, SEBDEN, 11b;

// set the IRQ tst to J2C routine
write chip_jtag,  IA0+irq_tst, lbl_TST_cpu0;   // set int_clr start addr for cpu0

cmd = 0000b;            // read at address 0
write srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
nop
wait 15
expect chip_jtag, srv_outdata, nw16 & 0xFF
expect chip_jtag, SMCMD, lp_state

cmd = 0001b;            // read at address 1
write chip_jtag, srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
nop
wait 15
expect chip_jtag, srv_outdata, (fault_ltc << 7) | (nw16 >> 8);
expect chip_jtag, SMCMD, lp_state

cmd = 0010b;            // read at address 2
write chip_jtag, srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
nop
wait 15
expect chip_jtag, srv_outdata, (fault_ltc << 7)
expect chip_jtag, SMCMD, lp_state

cmd = 0011b;            // read at address 3
write chip_jtag, srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
nop
wait 15
expect chip_jtag, srv_outdata, (fault_ltc << 7)
expect chip_jtag, SMCMD, lp_state

cmd = 0100b;            // read at address 4
write chip_jtag, srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
nop
wait 15
reg_j2c = t_parit_bit_o | (t_false_bit_o << 4);
expect chip_jtag, srv_outdata, reg_j2c
expect chip_jtag, SMCMD, lp_state

cmd = 0110b;            // read at address 6
write chip_jtag, srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
nop
wait 15
expect chip_jtag, srv_outdata, ver_cpld
expect chip_jtag, SMCMD, lp_state

// clear the counters and set the new spare & parity

reg_j2c = t_parit_bit | (t_false_bit << 4);

cmd = 1000b;            // write at address 0
data = reg_j2c;         // sel_s & sel_p
write chip_jtag, srv_command, cmd | (data << 4);
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
wait 15
expect chip_jtag, SMCMD, lp_state

write      NED,(root_flag << 14) | (oase_mode << 15) | (t_parit_bit << 10) | (t_false_bit << 6) | (t_ctrl_delay << 3) | t_strb_delay;

// restore the IRQ tst address => switch CPU clock off
write chip_jtag, IA0+irq_tst, lbl_LPW_cpu0;   // set int_clr start addr for cpu0
restrict 1
wait 1000;