include src/common/scsn_ids.tcs

const dutOri = chip_hm | chip_t3ab;

USE_J2C = 1;

const nwords = 63; //62; // max 63
const npackets = 117; //117; // 300

const mode_jtag = 01b;
const mode_rstn = 00b;
const mode_i2c  = 11b;
//const npackets = 1;

const cnt_mode = 0;
//const simple_test_n  = 0xFFFF; // or 0
//const simple_test_n  = 0xFFFF0000; // or 0
//const simple_test_n  = 0x0000FFFF; // or 0
const simple_test_n  = 0xFFFF;

const oase_mode  = 0; // 1 for OASE mode, then the strobe is clock (continuous)

const root_flag  = 1; // 1 for root, the TRAP starts sending independently

const L0time= 0x00004050;
const L1time= 0x00004230+100;    // the start of readout, no confirm, used only internally
const L2time= 0x00004230+24+100; // this is for ALICE the L1A

const nsig_tr = 0xAAAA;
const nsig_rr = 0x0000;
const irq_clr = 0;
const irq_acq = 2;
const irq_raw = 4;
const irq_tst = 1;

// all delays can be from 0 to 7

// all delays:    min .best. max
const ni_data_delay = 2; // 0..4 by strobe delay 6 or 0

const t_ctrl_delay  = ni_data_delay;  // not used here!!!

t_data_delay0 = ni_data_delay; //
t_data_delay1 = ni_data_delay; //
t_data_delay2 = ni_data_delay; //
t_data_delay3 = ni_data_delay; //
t_data_delay4 = ni_data_delay; //
t_data_delay5 = ni_data_delay; //
t_data_delay6 = ni_data_delay; //
t_data_delay7 = ni_data_delay; //
t_data_delay8 = ni_data_delay; //
t_data_delay9 = ni_data_delay; //

t_strb_delay = 0; //

const t_false_bit1  = 0; // 0..9
const t_parit_bit1  = 1; // 0..9

const t_false_bit2  = 8; // 0..9
const t_parit_bit2  = 9; // 0..9

restrict WAFER
// FPGA only
const xor_mask  = 0x3FF;
const and_mask  = 0x3FF;
const  or_mask  = 0x000;

const rst_inv = 0; // must be 0 if no additional reset inverter is soldered
const rst_opend = 1; // if open drain the pull up in the TRAP can be measured.
restrict 1

reg_j2c = t_parit_bit1 | (t_false_bit1 << 4);
//reg_j2c = t_false_bit1 | (12 << 4);
//                      if 10, PRBSEN of TLK2501 is high (test pattern in TLK)
//                      if 12, the CPLD sends a test pattern to the TLK2501
//                      if 14 then SD2ANL of the TLK2501 & LTC is 0

// IO addresses to communucate with any service program
const srv_command = 0xF0E0; // for the code of the operation and if enough for in/out data
const srv_indata  = 0xF0E1; // for input data, stored by the SCSN master
const srv_outdata = 0xF0F0; // for output data, stored by the TRAP program

// I2C devices
i2c_addr_ltc = 0x14;    // LTC chip
i2c_addr_eep = 0xAE;    // serial EEPROM chip
eep_write_time = 2000;  // us timedelay after write

lp_state = 0x200;
fault_ltc = 1;
eeprom_offs_addr = 0x60; // for 2401, for 2400 is not important
eeprom_offs_addr_ser = 0;
eeprom_offs_addr_PI  = 0x10;
ver_cpld = 4;

BYTE_5_sernr = 0x02;
BYTE_4_sernr = 0x06;
BYTE_3_sernr = 0x06;
BYTE_2_sernr = 0x62;
BYTE_1_sernr = 0x00;

BYTE_1_serPI = 0x00;