// NOT USED!!!
include src/chip_def.tcs
//include src/scsn_ids.tcs
include src/eeprom_params.tcs

include src/cpu1_labels.tcs

write chip_jtag,      IA1+irq_tst, lbl_TST_cpu1;   // set int_clr start addr for cpu0

const simdelay = 40;

// This part is for I2C2scsn

// at IO address srv_command is : device_address(7:0),
//                                start address (15:8),
//                                number_of_bytes(17:16),
//                                read/write (24-bit 1/0)

// ************ INIT I2C
write chip_jtag,      srv_command, 0; // init
pretrigger 6
wait simdelay ; // for simulation only
expect chip_jtag,      SMCMD, 0x00000300

// ***************************************************

restrict stop_LTC

// ************ to suppress stand alone operation of LTC5100 while programming the EEPROM
device_address = (0xA << 1);
number_of_bytes = 2;
start_address  = 0x10;
write chip_jtag,      srv_command, device_address | (start_address << 8) | (number_of_bytes << 16) | (0 << 24);
write chip_jtag,      srv_indata+0, 0x11;
write chip_jtag,      srv_indata+1, 0xFF;
// start
pretrigger 6
wait simdelay ; // for simulation only
wait -100000, 0, scheck;
expect chip_jtag,      SMCMD, 0x00000300



reg1 = 0x56;

reg2 = 0xAB;

// ************ WRITE (reg_1)
start_address  = 2 ;
number_of_bytes = 1

write dut, srv_command, device_address | (start_address << 8) | (number_of_bytes << 16) | (0 << 24);
write dut, srv_indata, reg1;

// start
pretrigger 6
wait simdelay ; // for simulation only
expect dut, SMCMD, 0x00000300


// ************ WRITE (reg_2)
start_address  = 1 ;
number_of_bytes = 1

write dut, srv_command, device_address | (start_address << 8) | (number_of_bytes << 16) | (0 << 24);
write dut, srv_indata, reg2;

// start
pretrigger 6
wait simdelay ; // for simulation only
expect dut, SMCMD, 0x00000300


// ************ READ (reg_1)
start_address  = 5
number_of_bytes = 1
write dut, srv_command, device_address | (start_address << 8) | (number_of_bytes << 16) | (1 << 24); // read

// start
pretrigger 6
wait simdelay ; // for simulation only
expect dut, SMCMD, 0x00000300
expect dut, srv_outdata, reg1

// ************ READ (reg_2)
start_address  = 6
number_of_bytes = 1
write dut, srv_command, device_address | (start_address << 8) | (number_of_bytes << 16) | (1 << 24); // read

// start
pretrigger 6
wait simdelay ; // for simulation only
expect dut, SMCMD, 0x00000300
expect dut, srv_outdata, reg2

write dut,      IA1+irq_tst, lbl_LPW_cpu1;   // set int_clr start addr for cpu0