include src/niscsn/chip_def_rob.tcs

const irq_tst = 1;
const irq_msk = (1 << irq_tst);
// start address IRQ1 - tst
write IA0+irq_tst, 0;
write IA1+irq_tst, 0;
write IA2+irq_tst, 0;
write IA3+irq_tst, 0;
// enable hardw IRQ tst
write IRQHW0, irq_msk
write IRQHW1, irq_msk
write IRQHW2, irq_msk
write IRQHW3, irq_msk
// set high level IRQ tst
write IRQHL0, irq_msk
write IRQHL1, irq_msk
write IRQHL2, irq_msk
write IRQHL3, irq_msk

// overwrite, the DBANK representing the errors encountered
write 0xF000, 0x0BAD
write 0xF001, 0x1BAD
write 0xF002, 0x2BAD

write 0xF040, 0x0BAD
write 0xF041, 0x1BAD
write 0xF042, 0x2BAD

write 0xF080, 0x0BAD
write 0xF081, 0x1BAD
write 0xF082, 0x2BAD

write 0xF0C0, 0x0BAD
write 0xF0C1, 0x1BAD
write 0xF0C2, 0x2BAD

write NTRO, 0x3FFFB; // CPU3 sends data
write NICLK, 7
write NIODE, 7;
write NIOCE, 7;
write NIIDE, 7;
write NIICE, 7;

write SMMODE, 0xF0E2