# DBANK
EvtCtr_DB                 0xf0f4  // used as an event counter, (c12)
ADCMSK_DB                 0xf0f5  // the content of the ADCMSK register, used for refresh
ChipPOS_DB                0xf0f6  // c14 was used for MCM id, readout flags
h_0_DB                    0xf0f7  // c15 was used for h_0 before
SMMODE_DB                 0xf0f8  // the content of the SMMODE register, used for refresh
NTRO_DB                   0xf0f9  // the content of the NTRO register: readout order tracklet mode, used for refresh
NRRO_DB                   0xf0fa  // the content of the NRRO register: readout order raw data readout mode, used for refresh
NED_DB                    0xf0fb  // the content of the NED  register: output excludes and control delays, used for refresh
NDLY_DB                   0xf0fc  // the content of the NDLY register: out data delays, used for refresh
NP0_3_DB                  0xf0fd  // bits 10..3 of NP0..3 registers (false & parity position), the lower bits 2..0 are 100 always, used for refresh
H_PAD_ROW_COL_DB          0xf0fe  // used internally to store the MCM tracklet header (without bits 24..1 with the HPID2..0). Do not initialize, use for control

# DMEM
Base_LUT_1divN_DM_SCSN    0xC000  // probably not used any more, Table with 2**31/N, N=0..31
WDOG_DM_SCSN              0xC060  // watch dog counter, set to about 20 when no tracklets, count down when tracklets. At 0 ignore the tracklets and refresh.
SCALE_Y_DM_SCSN           0xC061  // scale factor for position
OFFS_Y_DM_SCSN            0xC062  // offset for position
SCALE_D_DM_SCSN           0xC063  // scale factor for deflection
DEFL_CR_DM_SCSN           0xC064  // deflection correction, not used now
SCALE_Q_DM_SCSN           0xC065  // scale factor for the charge, used when DYN_FP_Q=0
ZS_SMSK_DM_SCSN           0xC068  // 64-bit, sample mask, used to ignore (bit=0) some samples in the event buffer indicators
ZS_ADC_ORM_DM_SCSN        0xC06A  // 21-bit, adc channel mask, used when ZS_ADCMSK_OR=1 to send unconditionally some selected ADC channels (bit=1)
AddrDMstat_DM_SCSN        0xC080  // RMS statistic block
DEFL_RNG_TBL_DM_SCSN      0xC020  // .. 0xC043, deflection range table (32-bit signed: min0, max0, min1, max1..., min17, max17), now initialized with the max range -127..+127 in all channels.
POS_LUT_TBL_DM_SCSN       0xC048  // .. 5D, position LUT, used for refresh
GAIN_TABLE_MULT_DM_SCSN   0xC11C  // 9-bit/channel, 3 channels in 32-bit, 21 channels -> 7 32-bit words
GAIN_TABLE_ADDT_DM_SCSN   0xC124  // 6-bit/channel, 5 channels in 32-bit, 21 channels -> 5 32-bit words

// position LUT stored in DMEM, in 32-bit words: each word has 6 x 5 bit LUT data
//   LUT32[ 0]=LUT5[0] | LUT5[1] << 5 | LUT5[2] << 10 | LUT5[3] << 15 | LUT5[4] << 20 | LUT5[5] << 25
//   ...
//   LUT32[21]=LUT5[126] | LUT5[127] << 5 | flags << 12 | counter << 16
//      where flags is a 2-bit counter, 0 - init state, 1, 2, 3 - first, second, third/3 refreshed
//      once read, 6 times write to GIO 21 times and the last time write only twice to GIO! 128 = 6*21 + 2



Registers that are NOT refreshed and are don't care:

EBPC, C08..11CPU0..3, C12..15CPUA, NTP, EBPC, FCW1..5, TPVT (when TPVBY=0 bypass),
TPCI0..3, FGFn and FGAn (when gain filter not used), FLLn (non-linearity correction, as normally not used),
PASA* (as normally not used), SADC* (as normally not used), IA0..3+unused_IRQ, IRQSW0..3, L0TSIM

TPLn, FGFn, FGAn use DMEM for refresh, in MCMs with bad DMEM this will not work!