// ***************************************************************************
// Program parameters
// ***************************************************************************

//include src/common/param_includes.tcs

// hc header field, some of them used in the normal chips!
//hc_0_raw_ver_spec_nr = 1; // 1 bit = const 1
//hc_0_add_hd_words    = 2; // 3 bits  0..2 implemented!!!

//ZSon     = 0;    // 1 or 0
//TCKL_DIS = 0;    // 1 or 0
//TST_PATT = 0;    // 1 or 0

// Test pattern # or options for ZS
// in ZS mode, OPT[0] disables sending of MCM header followed by an empty ADC Mask
//             OPT[2..1] = 1,2,3: send every 128/256/1024 event without suppression
// In test patter mode, OPT means;
// 0 : counter/rob/mcm/cpu
// 1 : pseudorandom gen 10bit for ADC data
// 2 : evncnt( 6)/sector+1(5)/chamber+1(3)/plane+1(3)/rob(3)/mcm(4)/cpu(2)/cnt++
// 3 : evncnt(12)/sector+1(5)/chamber+1(3)/plane+1(3)/rob(3)/mcm(4)/cpu(2)
// in non-ZS, non-TP mode, OPT[0] enables calculating the ADC statistics
//OPT      = 0;    // 0..7

// the major version is used in the assembler program
//hc_0_raw_ver_maj_nr = (TST_PATT << 6) | (ZSon << 5) | (TCKL_DIS << 4) | (OPT << 0);
//hc_0_raw_ver_min_nr = 0; // unused in the assembler program

const PASAPULSE=0;     // reduces power consumption if 0
const USE_J2C = 0;

// PASA Pulser Setup (0 to 255)
const pasa_pulse_height = 255;

//const DMDELA_VAL =  2;         // Nominal:2  used in DMDELA
//const DMDELS_VAL = 15;         // Nominal:15 used in DMDELS

//const arbiter_timing = 1101b;
//const ARBTIM_VAL = 1101b;


// enable/disable hamming correction used in MEMCOR
//hamming_imem = HAMMIM | (HAMMIM << 1) | (HAMMIM << 2) | (HAMMIM << 3);
//hamming_dmem = HAMMDM | (HAMMDM << 1) | (HAMMDM << 2) | (HAMMDM << 3);

//const MEMCOR_VAL = hamming_imem | (hamming_dmem << 4) | (HAMMDB << 8);
//const IRQHW_VAL = (1 << IRQ_ACQ) | (1 << IRQ_CLR) | (1 << IRQ_RAW) | (1 << IRQ_TST);
//const IRQHL_VAL = (1 << IRQ_ACQ) | (1 << IRQ_CLR) | (1 << IRQ_RAW) | (1 << IRQ_TST);

//const ADCDAC_VAL     = 00000b; // 5 bit





const nwords = 63;
const npackets = 300;

const mode_jtag = 01b;
const mode_rstn = 00b;
const mode_i2c  = 11b;

//reg_j2c = m_parit_bit | (m_false_bit << 4);
//reg4 = m_parit_bit;

//TX_ER   = 0; // bit 0
//TESTEN  = 0; // bit 1, not used in the new design
//ANLGEN  = 1; // bit 1
//PRBSEN  = 0; // bit 2, 1 for test
//LCKREFN = 0; // bit 3
//ENABLE  = 1; // bit 4
//LOOPEN  = 0; // bit 5
//EN      = 1; // bit 6
//ALL_OE  = 1; // bit 7
//
//reg5 = TX_ER | (ANLGEN << 1) | (PRBSEN << 2) | (LCKREFN << 3) | (ENABLE << 4) | (LOOPEN << 5) | (EN << 6) | (ALL_OE << 7);
//reg5 = m_false_bit;

// IO addresses to communucate with any service program
const srv_command = 0xF0E0; // for the code of the operation and if enough for in/out data
const srv_indata  = 0xF0E1; // for input data, stored by the SCSN master
const srv_outdata = 0xF0F0; // for output data, stored by the TRAP program

// I2C devices
i2c_addr_ltc = 0x14;    // LTC chip
i2c_addr_eep = 0xAE;    // serial EEPROM chip
eeprom_offs_addr = 0x60; // for 2401, for 2400 is not important
eeprom_offs_addr_ser = 0;
eeprom_offs_addr_PI  = 0x10;
ver_cpld = 4;

BYTE_5_sernr = 0x02;
BYTE_4_sernr = 0x06;
BYTE_3_sernr = 0x06;
BYTE_2_sernr = 0x62;
BYTE_1_sernr = 0x00;

BYTE_1_serPI = 0x00;


eep_write_time = 2000;  // us timedelay after write

lp_state = 0x0200;


fault_ltc = 1;

include src/common/param_main.tcs